SiC Outer Peripheral Structure With Stepped JTE Field Control
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face issues with breakdown voltage reliability due to electric field concentration at the edge termination region, where the voltage withstanding structure is shallow, leading to lower breakdown voltage and increased avalanche breakdown, and the challenge of forming p-type regions with different impurity concentrations at precise depths.
Innovation Solution
A silicon carbide semiconductor device with a spatial modulation JTE structure, where p-type and p−-type regions are formed at shallower depths than the trench gate structure, and a p+-type embedded region is used to mitigate electric field concentration, with steps in the p-type outer peripheral region arranged in ascending order towards the chip center, ensuring a stable breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the voltage withstanding structure is disposed shallowly in the edge termination region, then the manufacturing process is simplified, but electric field concentration occurs at the outer corner portions leading to reduced breakdown voltage
Solution Approach 1:
The patent transitions from a two-dimensional shallow voltage withstanding structure to a three-dimensional stepped structure that extends deeper into the semiconductor substrate. The outer peripheral region includes multiple steps with different depths, where the first step extends to a first depth and the second step extends to a second depth greater than the first depth, thereby distributing the electric field across multiple dimensional levels rather than concentrating it at a single shallow plane.
Solution Approach 2:
The patent applies different structural characteristics to different regions of the outer peripheral region. The first step and second step have different depths and are disposed at different locations, with the second step having greater depth to specifically address electric field concentration at outer corner portions. This localized differentiation allows the structure to maintain manufacturing simplicity in less critical areas while providing enhanced breakdown voltage protection where needed.
2Reliability
If multiple p-type regions with different impurity concentrations are disposed adjacently, then the breakdown voltage is maintained, but positioning accuracy becomes difficult
Solution Approach 1:
The patent divides the outer peripheral region into distinct stepped sections rather than attempting to create continuously varying impurity concentrations. The first step and second step are separated into discrete structural units with clear boundaries, making it easier to position and manufacture each segment independently while maintaining the overall gradient effect for breakdown voltage control.
Solution Approach 2:
Instead of relying solely on precise lateral positioning of multiple p-type regions with different impurity concentrations, the patent uses the vertical dimension (depth) to create differentiation. The stepped structure with varying depths provides a clear geometric reference that simplifies positioning, while the depth variation itself serves to modulate the electric field distribution and maintain breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the breakdown voltage reliability by reducing electric field concentration and maintaining a higher breakdown voltage in the edge termination region, comparable to the active region, while simplifying the fabrication process by forming regions with the same impurity concentration and depth.
Implementation Method 1
the plurality of extension portions are arranged in descending order of proximity thereof to the end of the semiconductor substrate in the depth direction from the first main surface, thereby forming a plurality of steps that are recessed stepwise from an outer end of the outer end portion toward the center of the semiconductor substrate
Implementation Method 2
the JTE regions are disposed in descending order of impurity concentration thereof, in a direction from an inner side (center portion (chip center) side of the semiconductor substrate) to an outer side (end (chip end) side of the semiconductor substrate). Electric field strength tends to decrease in a direction from the active region to the chip end.
Data Source
AI summary
An active region has, in a periphery thereof, a p-type outer peripheral region that has sequentially from a front surface of a semiconductor substrate, a p++-type contact extension portion, a p-type base extension portion, and an upper portion and a lower portion of a p+-type extension portion, so as to form, at an outer end portion thereof, steps that are recessed stepwise toward a center of the active region and that in a depth direction, are arranged in ascending order of proximity thereof to the center. An innermost JTE region configuring a voltage withstanding structure contacts an outer end portion of the contact extension portion. Beneath the JTE region, a p+-type embedded region is provided at a same depth as the lower portion of the extension portion so as to be apart from the JTE region and the outer peripheral region and surround the periphery of the active region.