SiC Substrate Grinding for Low Resistance Bonding
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Solution Overview
Problem
The challenge in manufacturing front-to-back conductive semiconductor devices is the variability in electrical resistance between the semiconductor substrate and electrode due to surface unevenness during thinning, which leads to inadequate bonding and reduced mechanical strength, causing chip breakage during mounting or under load.
Innovation Solution
A method involving controlled grinding of the SiC substrate using abrasives with specific grain sizes (1 μm to 5 μm) followed by laser irradiation for electrical connection and additional electrode deposition, ensuring a thickness of 50 μm to 150 μm to establish stable bonding and reduce energization loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the semiconductor substrate is thinned to reduce energization loss, then the electrical resistance decreases and energy efficiency improves, but the surface unevenness increases causing variable electrical resistance between substrate and electrode
Solution Approach 1:
The patent changes the parameter of substrate thickness to 50-150 μm, which is an optimized range that balances energy loss reduction with maintaining adequate bonding area. This parameter optimization resolves the contradiction by finding the sweet spot where thinning reduces resistance but excessive thinning is avoided.
Solution Approach 2:
The patent applies preliminary grinding processing to the back surface of the substrate before electrode formation. This preliminary action creates a controlled uneven surface structure that increases the bonding area between substrate and electrode, compensating for the surface unevenness that occurs during thinning while maintaining low electrical resistance.
2Loss of energy
If the semiconductor substrate is ground for thinning, then the substrate thickness is reduced to lower resistance, but crystal defects occur reducing chip strength
Solution Approach 1:
The patent optimizes the substrate thickness parameter to remain within 50-150 μm after thinning, avoiding excessive thinning that would cause severe crystal defects. This parameter control maintains adequate mechanical strength while achieving the resistance reduction needed for low energy loss.
Solution Approach 2:
The patent performs preliminary grinding to create a controlled surface structure before final thinning. This preliminary action prepares the substrate in a way that reduces the impact of subsequent thinning operations, minimizing crystal defects and maintaining chip strength while still achieving the desired resistance reduction.
3Manufacturing precision
If the contact area between substrate and electrode varies due to ground-surface unevenness, then bonding quality becomes inconsistent, but electrical resistance varies affecting device performance
Solution Approach 1:
The patent applies preliminary grinding to the back surface before electrode deposition. This preliminary action creates a controlled surface topology that, when combined with the optimized substrate thickness, ensures consistent contact area between substrate and electrode. The result is uniform bonding quality and consistent electrical resistance across all devices.
Solution Approach 2:
The patent optimizes the substrate thickness parameter to 50-150 μm, which provides adequate mechanical support while maintaining a large enough bonding area even with surface unevenness. This parameter control ensures that variations in surface topology do not lead to significant variations in electrical resistance or bonding quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves excellent bonding and high mechanical strength with reduced energization loss by controlling substrate thickness and abrasive grain size, minimizing grinding damage and crystal defects.
Implementation Method 1
grinding a back-surface side of the SiC substrate, using an abrasive having an average abrasive grain size of not less than 1 μm and not more than 5 μm
Implementation Method 2
electrically connecting the first main electrode with the electrode bonding region by using laser irradiation
Data Source
AI summary
Included herein are, a step of forming an active region for a semiconductor device on a front surface of a SiC substrate, a step of forming a SiC substrate-to-drain electrode bonding region on a back surface of the SiC substrate by grinding it using an abrasive whose average abrasive grain size is within a specified range, a step of depositing a film of a first drain electrode on the SiC substrate-to-drain electrode bonding region, a step of electrically connecting the first drain electrode with the SiC substrate-to-drain electrode bonding region, and a step of depositing a film of a second drain electrode on the first drain electrode, so that a SiC semiconductor device having a high mechanical strength with a reduced energization loss is achieved.