SiC Transistor Orientation on Crystal Faces
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Solution Overview
Problem
Semiconductor devices using silicon carbide (SiC) face challenges in achieving optimal switching characteristics and integration due to the limited performance of transistors on specific crystal faces, particularly the (000-1) face, where p-type field effect transistors (p-FETs) do not operate normally, and carrier mobility is lower than n-type FETs on other faces.
Innovation Solution
The semiconductor device incorporates transistors with conductivity types appropriate to their respective crystal faces, with n-channel MOSFETs on the (000-1) face and p-channel MOSFETs on orthogonal (11-20) faces, allowing for improved performance and integration by optimizing channel width directions and epitaxial growth stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistors are integrated on a single crystal face (e.g., (000-1) face), then manufacturing process is simplified, but p-type FETs cannot operate normally and carrier mobility is limited
Solution Approach 1:
The patent transitions from a two-dimensional integration approach (all transistors on one crystal face) to a three-dimensional approach by utilizing multiple crystal faces (both (000-1) face and (11-20) face) of the SiC substrate. This allows n-type FETs to be formed on the (000-1) face while p-type FETs are formed on the (11-20) face, resolving the operational reliability issue without compromising manufacturing feasibility.
Solution Approach 2:
The patent applies different transistor types to different crystal faces based on their specific electrical characteristics. n-type FETs are placed on the (000-1) face where they exhibit good performance, while p-type FETs are placed on the (11-20) face where they can operate normally. This local optimization of transistor placement according to crystal face properties resolves the contradiction between manufacturing simplicity and device reliability.
2Ease of manufacture
If all transistors are formed on the (000-1) crystal face, then manufacturing is easier, but carrier mobility is lower and switching characteristics are degraded
Solution Approach 1:
The patent optimizes carrier mobility by placing transistors on different crystal faces according to their conductivity type requirements. n-type FETs on the (000-1) face and p-type FETs on the (11-20) face both achieve their optimal carrier mobility characteristics, resolving the contradiction between manufacturing ease and speed performance.
Solution Approach 2:
By utilizing the third dimension of crystal face orientation, the patent enables both n-type and p-type FETs to achieve high carrier mobility on their respective optimal faces, thereby improving overall switching characteristics without sacrificing manufacturing simplicity.
3Productivity
If CMOS circuits are integrated with high density, then device functionality is improved, but occupied area increases and mass production stability decreases
Solution Approach 1:
The patent achieves high-density CMOS integration by optimizing the spatial arrangement of n-type and p-type FETs on different crystal faces. This local optimization allows for more efficient packing of complementary transistor pairs, improving integration level while reducing the total occupied area and enhancing mass production stability.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first and a second transistor. The first transistor includes a first and a second region of a first conductivity type and a third region of a second conductivity type. The first region is disposed along a first crystal face of a silicon carbide region. The silicon carbide region has the first crystal face and a second crystal face. The second and the third region are disposed along the first face. The third region is provided between the first and the second region. The second transistor includes a fourth and fifth region of the second type and a sixth region of the first type. The fourth, the fifth and the sixth region are disposed along the second face of the silicon carbide region. The sixth region is provided between the fourth and the fifth region.