SiC Trench Layout for Parasitic Diode Suppression
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Solution Overview
Problem
Silicon carbide semiconductor devices face challenges in preventing the parasitic diode from turning on during off-states, leading to characteristic deterioration due to hole injection and stacking fault extension, which affects their performance in high-voltage and large-current applications.
Innovation Solution
The silicon carbide semiconductor device incorporates a transistor portion and a diode portion alternately arranged along the trench direction, with the diode portion configured to clamp voltage and reduce hole injection, and a staggered structure is implemented to further suppress parasitic diode turning on, thereby reducing the extension of stacking faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a parasitic Schottky barrier diode is provided in parallel to a parasitic pn diode, then the parasitic Schottky barrier diode can be turned on before the parasitic pn diode, but this increases device complexity and does not sufficiently suppress hole injection
Solution Approach 1:
The device is divided into distinct transistor portions and diode portions that are alternately arranged in a staggered configuration. Each portion has specific functions: transistor portions for switching and diode portions for clamping. This segmentation allows the parasitic diode suppression function to be distributed across multiple specialized regions rather than relying on a single complex structure.
Solution Approach 2:
The drift region serves as an intermediary between the source/drain regions and the substrate. By controlling the electric field distribution in this intermediate region through the staggered structure, the patent prevents direct hole injection into the substrate while allowing the parasitic diode to clamp voltage at appropriate levels.
2Reliability
If voltage clamping is implemented to reduce hole injection, then characteristic deterioration is suppressed, but the electric field distribution becomes concentrated leading to stacking fault extension
Solution Approach 1:
The patent transitions from a single-layer planar structure to a staggered three-dimensional arrangement where diode portions and transistor portions are offset relative to each other. This dimensional change distributes the electric field concentration across multiple spatial locations and depth levels, preventing localized field intensity that would cause stacking faults while maintaining overall voltage clamping functionality.
Solution Approach 2:
The electric field distribution parameters are changed by adjusting the positions, depths, and spacing of the alternately arranged transistor and diode portions. This parameter optimization allows the electric field to be distributed more evenly throughout the drift region, reducing peak field intensity that causes stacking faults while maintaining effective voltage clamping to prevent hole injection.
3Reliability
If a staggered structure is implemented to suppress parasitic diode turning on, then hole injection is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent combines multiple functions into the staggered structure: voltage clamping, hole injection suppression, and electric field distribution are all achieved through the same alternating arrangement of transistor and diode portions. This merging reduces the need for separate structures and simplifies manufacturing by using a unified formation process for both portion types, thereby reducing precision requirements compared to multi-step alignment processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the turning on of parasitic diodes, reduces hole injection, and prevents characteristic deterioration, enhancing the device's performance and reliability in high-voltage and large-current applications by controlling the electric field and avalanche currents.
Implementation Method 1
the diode portion configured to clamp voltage and reduce hole injection
Implementation Method 2
by providing a parasitic Schottky barrier diode in parallel to a parasitic pn diode between a source and a drain, the parasitic Schottky barrier diode can be turned on before the parasitic pn diode is turned on
Implementation Method 3
a staggered structure is implemented to further suppress parasitic diode turning on, thereby reducing the extension of stacking faults
Data Source
AI summary
Provided is a silicon carbide semiconductor device comprising a transistor portion and a diode portion, comprising: a semiconductor substrate; a plurality of trench portions that are provided on a front surface of the semiconductor substrate; a drift region of a first conductivity type that is provided on the semiconductor substrate; and a second conductivity type region that covers a side wall and a bottom of a trench portion in the diode portion; wherein the transistor portion and the diode portion are alternately arrayed along an extending direction of the trench portion in a mesa portion that is sandwiched between the plurality of trench portions.