SiC Trench Gate Drift Layer Layout for Low On-Resistance
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Solution Overview
Problem
Power transistors with trench gate structures using silicon carbide (SiC) substrates face challenges in reducing on-resistance while maintaining high breakdown voltage, as increasing one parameter often deteriorates the other, making it difficult to simultaneously achieve both improved performance and reliability.
Innovation Solution
The semiconductor device incorporates a silicon carbide substrate with a specific layer structure, including n-type semiconductor layers and p-type impurity regions, where the n-type semiconductor layer with higher impurity concentration is formed between p-type impurity regions and beneath the gate electrode, optimizing the distance and impurity concentrations to reduce on-resistance and enhance breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the impurity concentration of the drift layer is increased to reduce on-resistance, then the on-resistance decreases, but the breakdown voltage deteriorates
Solution Approach 1:
The patent applies local quality by creating distinct regions with different impurity concentrations within the drift layer. Specifically, it forms a high-concentration n-type semiconductor layer (second semiconductor layer) between lower-concentration n-type layers (first and third semiconductor layers). This local variation in impurity concentration allows the device to achieve low on-resistance in the high-concentration region while maintaining adequate breakdown voltage through the lower-concentration regions, thus resolving the contradiction between reducing on-resistance and maintaining breakdown voltage.
2Reliability
If the trench gate structure is used to improve breakdown voltage, then the breakdown voltage improves, but the on-resistance increases
Solution Approach 1:
The patent applies parameter changes by systematically varying the impurity concentration parameter across different regions of the drift layer. The first semiconductor layer has a first impurity concentration, the second semiconductor layer has a higher second impurity concentration, and the third semiconductor layer has a third impurity concentration. By optimizing these concentration parameters and their spatial distribution, the patent achieves both low on-resistance (through the high-concentration second layer) and high breakdown voltage (through the trench gate structure combined with the graded concentration profile), thereby resolving the contradiction between these two parameters.
Data Source
AI summary
A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.