SiC Trench Gate Channel Threshold and Leakage Control
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face challenges in suppressing leakage between the source and drain during reverse bias, and in achieving high channel threshold without decreasing electron mobility, due to limitations in p-type base region concentration and implantation techniques.
Innovation Solution
The silicon carbide semiconductor device incorporates a trench gate structure with a p-type base region, a high-concentration channel implantation layer, and strategically positioned n-type and p-type regions to increase the channel threshold and reduce leakage, while maintaining electron mobility, by using ion implantation and epitaxial growth techniques to form regions with specific impurity concentrations and geometries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the p-type base region concentration is increased to suppress leakage between source and drain during reverse bias, then leakage is reduced, but electron mobility decreases and channel threshold cannot be sufficiently increased
Solution Approach 1:
The patent applies local quality by creating distinct regions with different impurity concentrations: a first p-type region with higher concentration near the gate insulating film for leakage suppression, and a second p-type region with lower concentration for maintaining electron mobility. This spatial differentiation of material properties resolves the contradiction between leakage suppression and mobility maintenance.
Solution Approach 2:
The patent segments the base region into multiple p-type regions with different characteristics. The first p-type region (higher concentration) handles leakage suppression locally near the gate, while the second p-type region (lower concentration) maintains overall electron mobility. This segmentation allows each region to optimize for its specific function without compromising the other.
2Reliability
If ion implantation is performed to increase channel threshold, then leakage is suppressed, but electron mobility decreases
Solution Approach 1:
The patent uses local quality by performing ion implantation selectively in the first p-type region near the gate insulating film rather than uniformly across the entire channel. This localized implantation increases channel threshold and suppresses leakage only where needed, while preserving electron mobility in the broader channel region.
3Productivity
If a trench gate structure is used to increase unit cell density and current density, then cost efficiency improves, but leakage between source and drain increases
Solution Approach 1:
The patent addresses the trench gate leakage issue by creating a first p-type region with higher impurity concentration specifically at the corner portions of the trench gate structure where leakage-prone electric field concentration occurs. This localized high-concentration region suppresses leakage at critical points while maintaining the high unit cell density benefits of the trench gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances channel mobility, reduces ON resistance, and suppresses leakage, enabling efficient switching and reduced conduction loss while maintaining high threshold voltages.
Implementation Method 1
by using ion implantation and epitaxial growth techniques to form regions with specific impurity concentrations and geometries
Implementation Method 2
by using ion implantation and epitaxial growth techniques to form regions with specific impurity concentrations and geometries
Data Source
AI summary
A semiconductor device has: a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a first semiconductor region of a second conductivity type; a second semiconductor region of the first conductivity type; a trench; a gate insulating film; a gate electrode; a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type. The third semiconductor region is provided between the gate insulating film on a sidewall of the trench and the first semiconductor region. The fourth semiconductor region is provided between the first semiconductor region and the third semiconductor region, and has an impurity concentration higher than that of the first semiconductor region.