SiC Trench Gate Mesa Layout for Higher Channel Width Density
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Solution Overview
Problem
Silicon carbide (SiC) trench gate power transistors face challenges with high electric fields on the gate insulator, limiting channel width density due to the dielectric strength of SiC and the need for protective regions that restrict channel width further.
Innovation Solution
A silicon carbide semiconductor device design featuring a drift layer, doped regions, and a gate trench structure that divides the drift layer into mesas with leg portions, increasing channel width density while maintaining proper grounding and dielectric insulation to mitigate high electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If trench gate structure is used to increase channel width density, then channel width density is improved, but gate insulator experiences higher electric field which compromises dielectric integrity
Solution Approach 1:
The drift layer is divided into multiple mesas by forming gate trenches that segment the continuous drift region into discrete floating mesas. This segmentation allows the gate insulator to be positioned at the perimeter of each mesa where electric field concentration is reduced, while still maintaining high channel width density through the cumulative effect of multiple mesas.
Solution Approach 2:
The gate insulator is strategically positioned at specific locations (perimeter of mesas) where the electric field distribution is most favorable. By localizing the gate insulator to these specific regions rather than uniformly distributing it, the design maintains dielectric integrity while maximizing channel width density in the active regions.
2Reliability
If p+ protecting regions are added around trench bottom to protect gate insulator, then gate insulator protection is improved, but channel width density is limited
Solution Approach 1:
Instead of adding protecting regions in the lateral plane around the trench bottom (2D approach), the invention extends the protection vertically by forming p+ protecting regions at the bottom of the gate trench that extend into the drift layer. This vertical extension provides protection without consuming lateral space, thereby maintaining channel width density.
Solution Approach 2:
The p+ protecting regions are nested within the gate trench structure, extending from the trench bottom into the drift layer. This nested configuration allows the protecting regions to be integrated into the existing trench gate structure without adding external structures that would limit channel width density.
3Reliability
If source contacts are designed to connect source and body regions, then electrical connectivity is improved, but channel width density is limited
Solution Approach 1:
The drift layer is segmented into multiple mesas, and source contacts are positioned at specific locations on these mesas. This segmentation allows source contacts to be strategically placed to maintain electrical connectivity while minimizing their impact on the overall channel width density, as each mesa can independently support source contact configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances channel width density and performance by increasing the total channel width without violating manufacturing design rules, improving upon conventional trench gate transistors.
Implementation Method 1
a gate electrode arranged in the gate trench and dielectrically insulated from the first doped region, the second doped region and the drift layer by a gate insulator
Implementation Method 2
Silicon carbide (SiC) as an emerging semiconductor material for power devices provides superior properties including high dielectric strength to the electric field
Data Source
AI summary
A silicon carbide semiconductor device includes a drift layer, a first doped region, a second doped region, a gate trench, a third doped region and a gate electrode. The drift layer is disposed on a SiC substrate. The first doped region is disposed on the drift layer. The second doped region is disposed on the first doped region. The gate trench is extended from an upper surface of the second doped region through the first doped region and into the drift layer. The gate trench is formed in a manner dividing the drift layer into a plurality of mesas encircled by the gate trench, each of the mesas comprises a center portion and a plurality of leg portions extended from the center portion. The third doped region is arranged in the center portion of the mesa, and is disposed in the first doped region and adjacent to the second doped region. The gate electrode is arranged in the gate trench and dielectrically insulated from the first doped region, the second doped region and the drift layer by a gate insulator.