SiC VJFET Non-Uniform Channel Doping for Low Resistance and High Voltage Blocking
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Solution Overview
Problem
Junction field-effect devices face a trade-off between low on-state channel resistance and high voltage-blocking gain, with existing solutions either having high channel resistance and low voltage-blocking gain or vice versa, particularly in power SiC VJFETs, which impairs the development of normally-off switching devices.
Innovation Solution
A semiconductor device with a non-uniformly doped channel structure, featuring a 'VTH-control' portion with a lower average dopant concentration and a 'field-stop' portion with a higher average dopant concentration, allowing for reduced channel resistance and enhanced voltage-blocking capability, achieved through selective etching and dopant implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If a short-channel JFET or SIT structure is used, then the channel resistance is reduced, but the voltage-blocking gain becomes small
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping profile within the channel, where the dopant concentration varies along the channel length. Specifically, the channel has a first region with a first dopant concentration and a second region with a second dopant concentration, allowing different sections to serve different functions: one region optimizes for low resistance while the other maintains voltage blocking capability.
Solution Approach 2:
The patent changes the dopant concentration parameter along the channel length to resolve the contradiction. By varying the dopant concentration from one region to another, the patent achieves both low channel resistance in one region and high voltage-blocking gain in another region, rather than using a uniform doping profile.
2Reliability
If a long channel enhancement-mode JFET is used, then the voltage-blocking gain is high, but the channel current saturates early
Solution Approach 1:
The patent divides the channel into regions with different doping characteristics, where one region is optimized for voltage blocking (higher dopant concentration) and another region is optimized for current conduction (lower dopant concentration). This local differentiation allows the channel to maintain high voltage-blocking gain while preventing early current saturation through the presence of the lower-doped region.
Solution Approach 2:
The patent varies the dopant concentration parameter along the channel to prevent early current saturation. By having a region with lower dopant concentration, the patent extends the linear region operation and delays current saturation, thereby improving productivity while maintaining high voltage-blocking gain in the higher-doped region.
3Reliability
If the channel is pinched-off by threshold voltage, then the device can block maximum voltage, but the on-state channel resistance increases
Solution Approach 1:
The patent creates different regions within the channel with different doping concentrations to simultaneously achieve voltage blocking and low resistance. The higher-doped region provides low on-state resistance when the channel is pinched-off, while the lower-doped region maintains the voltage-blocking capability, resolving the contradiction between these two requirements.
Solution Approach 2:
By changing the dopant concentration parameter along the channel length, the patent enables the channel to exhibit both low resistance characteristics in the on-state and high voltage-blocking capability when pinched-off. The non-uniform doping profile allows different sections to optimize for different operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The non-uniformly doped channel structure enables the device to achieve low on-state resistance and high voltage-blocking gain, effectively addressing the limitations of existing devices by allowing the channel to be pinched-off at the threshold voltage while maintaining low total device resistance.
Implementation Method 1
the first average dopant concentration is lower than the second average dopant concentration and wherein the second average dopant concentration is higher than the average dopant concentration of the first layer
Implementation Method 2
a non-punch-through (NPT) channel structure with significantly reduced resistance
Data Source
AI summary
Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.