SiC VJFET Self-Aligned Gate Reduces Leakage
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Solution Overview
Problem
Existing methods for manufacturing vertical channel silicon carbide junction field effect transistors face challenges in achieving uniform p+ sidewall doping, leading to non-uniform channel width and increased complexity and cost, particularly due to the need for angled ion implantation and multiple energy implants, which result in high gate-source leakage under reverse bias.
Innovation Solution
A semiconductor device with tapered sidewalls and offset implanted gate regions, where the p+ gate is self-aligned and offset from the n+ source, using techniques such as conformal or non-conformal implant masks and thermal oxidation to minimize gate-source junction leakage, allowing for more controlled channel width and reduced electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If normal incident ion implantation is used to dope sidewalls, then the manufacturing process is simple, but the doping is non-uniform with low dopant concentration
Solution Approach 1:
The patent introduces a third dimension by creating raised regions (ridges) on the substrate surface before implantation. This topographic feature causes the ion implantation beam to naturally angle onto the sidewalls, achieving uniform doping without requiring wafer rotation or multiple implantation steps. The raised regions act as a geometric guide that converts normal incident implantation into effective sidewall doping.
2Manufacturing precision
If angled ion implantation is used to dope sidewalls, then sidewall doping uniformity improves, but the manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent performs preliminary formation of raised regions (through epitaxial growth or other deposition methods) before the ion implantation step. This preliminary topographic preparation enables subsequent simple normal-incident implantation to achieve what would otherwise require complex angled implantation. The raised regions are prepared in advance to guide the implantation process.
Solution Approach 2:
The patent replaces the mechanical complexity of wafer rotation and angled beam positioning with a static geometric feature (raised regions). Instead of dynamically adjusting the implantation angle through wafer manipulation, the fixed topography passively directs the implantation ions onto the sidewalls at the appropriate angles.
3Manufacturing precision
If multiple energy implants are used for SiC sidewall doping, then doping uniformity is achieved, but the manufacturing time and cost increase
Solution Approach 1:
By introducing the vertical dimension through raised regions, the patent enables single-energy implantation to achieve uniform sidewall doping. The geometric configuration of the raised regions ensures that ions implanted at normal incidence naturally strike the sidewalls at angles that produce uniform doping profiles, eliminating the need for multiple energy steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces gate-source leakage under reverse bias and maintains low drain-induced barrier lowering, enabling the device to block high voltages while minimizing static power dissipation and residual implant damage.
Implementation Method 1
selectively implanting ions into a channel layer of a semiconductor material of a first conductivity type to form implanted gate regions
Implementation Method 2
the first and second sidewalls of the raised regions adjacent the lower surface are tapered inward and form an angle of at least 5° from vertical
Implementation Method 3
using techniques such as conformal or non-conformal implant masks and thermal oxidation to minimize gate-source junction leakage
Data Source
AI summary
A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.