3C-SiC Carrier Wafer Growth for Low Bow and Warp
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Solution Overview
Problem
The production of large and thin SiC carrier wafers is expensive due to high bow and warp caused by internal stresses, and existing methods result in slow growth rates and formation of short crystallites, making them costly and inefficient.
Innovation Solution
A method involving a CVD process to grow SiC carrier wafers with a 3C crystal structure, incorporating nitrogen-doped crystallites exceeding 5 μm in length, which are radially grown to compensate for internal tensions, resulting in a bow and warp of less than 50 μm, and a composite substrate bonded with a monocrystalline SiC wafer for enhanced stability and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epitaxy is used to produce thin and large size SiC carrier wafers, then the wafer quality is improved, but the production cost increases and production speed decreases
Solution Approach 1:
The patent changes the crystal structure parameter from conventional 4H-SiC to 3C-SiC, enabling faster growth rates while maintaining wafer quality. This parameter change allows the production of thin and large size carrier wafers without the slow growth speed limitation of epitaxy, resolving the contradiction between quality and productivity.
2Productivity
If the wafer surface size is increased, then the productivity is improved, but the bow and warp increase due to internal stresses
Solution Approach 1:
The patent applies local quality by creating a specific crystallite size distribution where larger crystallites (greater than 5 μm) are positioned to compensate for internal tensions in specific regions of the wafer. This local structural optimization reduces bow and warp while maintaining large wafer surface size, resolving the contradiction between productivity and shape stability.
3Manufacturing precision
If the temperature range is set between 1300°C and 1400°C, then the crystal structure is improved, but the growth speed decreases and crystallite length is limited
Solution Approach 1:
The patent changes the temperature parameter and pressure conditions to enable the formation of 3C-SiC crystal structure with faster growth rates. This parameter change allows crystallites to grow longer than 5 μm while maintaining high growth speed, resolving the contradiction between crystal structure quality and growth speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method produces cost-effective, crack-free SiC carrier wafers with improved electrical conductivity and reduced warping, utilizing a CVD process that enhances deposition rates and reduces the need for post-processing, thereby lowering production costs.
Implementation Method 1
growing a SiC solid, in particular to a diameter of at least 7.5 cm or to a cross-sectional area size orthogonal to the length direction of the SiC growth substrate of at least 44.17 cm2, by depositing SiC on the deposition surface in the CVD reactor
Data Source
AI summary
A SiC carrier wafer has a diameter of at least 7.5 cm and a height between 200 μm and 500 μm. The wafer includes an inner section and an outer section. The outer section surrounds the inner section and the inner section includes a part of a SiC growth substrate. The inner section is formed by a crystal structure that is predominantly formed by a 3C crystal structure. The outer section is formed by a crystal structure predominantly formed by a 3C crystal structure and includes crystallites extending in length direction of the individual crystallite of more than 5 μm. A bow of the wafer is less than 50 μm and a warp of the wafer is less than 50 μm. The crystal structure of the inner section and the crystal structure of the outer section are Nitrogen doped and have an electric resistivity less than 0.03 Ohm-cm.