Side-Capacitor ROM Cell Layout for High Capacitance in Small Area
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Solution Overview
Problem
Conventional non-volatile memory devices occupy large areas due to the placement of capacitors, leading to increased costs and inefficiencies in programming and erasing operations.
Innovation Solution
A small-area side-capacitor read-only memory device is designed with conductive gates overlapping dielectric layers to create a capacitance effect, using finger portions to minimize layout area and enable efficient reading and writing, and a method for operating the memory array that allows simultaneous programming and erasing of multiple memory cells at specific bias voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional non-volatile memory structure with separate capacitors is used, then the memory can store charges effectively, but the area occupied by each memory cell increases significantly
Solution Approach 1:
The patent merges the capacitor and transistor into a single integrated structure where the conductive gate of the transistor serves dual purposes: as the transistor gate and as one plate of the capacitor. The dielectric layer formed between the conductive gate and the ion-doped area creates the capacitance function, eliminating the need for a separate capacitor structure. This integration directly resolves the area occupation problem while maintaining charge storage capability.
Solution Approach 2:
The conductive gate is designed to perform multiple functions simultaneously: it acts as the control gate for the field-effect transistor and as the storage electrode for the capacitor. This multi-functionality allows the memory cell to achieve both transistor switching capability and charge storage capability within a single structural element, thereby reducing the overall memory cell area.
2Productivity
If more memory cells are programmed simultaneously using high voltage, then the programming speed increases, but the current consumption and voltage requirements increase
Solution Approach 1:
The patent transitions from conventional planar voltage application to a vertical field configuration where high voltage is applied across the thickness of the dielectric layer in the stacked structure. This dimensional change allows the electric field to be concentrated in the vertical direction through the dielectric, enabling effective charge injection and programming with reduced lateral current spread and lower overall power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the overall area of the memory device, decreases production costs, and enhances the efficiency of writing and erasing operations by applying high voltages to capacitors and transistors, allowing for simultaneous programming and erasing of numerous memory cells without additional isolating transistors.
Implementation Method 1
employ areas where conductive gates overlap dielectric layers to produce a capacitance effect
Implementation Method 2
The first ion-doped areas are respectively used as a source and a drain. The second ion-doped area and the first ion-doped areas are doped with ions that have the same conductivity type.
Data Source
AI summary
A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.