Side Wettable Plating for Semiconductor Chip Packages
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Solution Overview
Problem
Flat no-leads semiconductor packages, such as DFN and QFN, face challenges in achieving good solder connections and visual inspection due to uncoated side lead lands during singulation, which can lead to oxidation and inconsistent solderability, making it difficult to manufacture smaller, thinner, and cost-effective packages with improved thermal performance.
Innovation Solution
The method involves singulating semiconductor chip packages, immersing them in a plating solution, contacting lead lands with conductive material, and electrolytically plating both side and bottom land portions to create a solder wettable surface, ensuring consistent solderability and ease of visual inspection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flat no-leads packages are manufactured in block format and singulated, then productivity and cost-effectiveness are improved, but side lead lands become uncoated and oxidize, worsening solderability and reliability
Solution Approach 1:
The patent applies preliminary plating action by coating the side lead lands with solder wettable material before the singulation process. This ensures that when packages are separated from the block, the side surfaces already have protective solderable coating, preventing oxidation and ensuring reliable solder connections without requiring post-singulation plating operations.
Solution Approach 2:
The patent changes the plating process parameters by using electrolytic plating with specific solutions (such as tin-based or lead-free solder alloys) applied under controlled electrical conditions. This creates a uniform, adherent solder wettable layer on the side lead lands that maintains solderability through the manufacturing process.
2Ease of manufacture
If side lead lands are not coated with solder wettable material, then manufacturing process is simpler, but visual inspection of solder connections becomes difficult, worsening measurement capability
Solution Approach 1:
The patent utilizes the visual properties of solder material (typically shiny, metallic appearance) deposited on side lead lands to enable visual inspection. The solder wettable coating creates a distinct visual contrast that allows inspectors to easily detect proper solder fillet formation, wetting, and connection quality on the side surfaces of the package.
3Temperature
If exposed thermal pad is provided for direct soldering, then thermal performance is improved, but side portions require additional coating to achieve consistent solderability, worsening manufacturing complexity
Solution Approach 1:
The patent merges the plating operations by applying solder wettable material to both the exposed thermal pad and the side lead lands in a single integrated electrolytic plating process. This combined approach ensures consistent coating across all solderable surfaces while maintaining process efficiency, avoiding the need for separate plating steps for different surfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides reliable and inspectable solder joints with improved thermal performance, enabling the production of smaller, cost-effective semiconductor packages suitable for various industries by ensuring both side and bottom land portions are coated with solder wettable material.
Implementation Method 1
electrolytically plating the lead land of the semiconductor chip package
Data Source
AI summary
A method for providing a semiconductor chip package with side wettable plating includes singulating a semiconductor chip package from an array of packages formed in a block format, immersing the semiconductor chip package in a bath of plating solution, contacting a lead land of the semiconductor chip package with conductive contact material within the bath of plating solution, connecting the conductive contact material to a cathode electrical potential, connecting an anode within the bath of plating solution to an anode electrical potential, and plating the lead land of the semiconductor chip package.