Conductive Feature Sidewall Capping for Air-Gap Interconnects

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Solution Overview

Problem

The challenge in semiconductor manufacturing is to form conductive features with low resistance and high thermal stability while minimizing deformation and parasitic capacitance, which is exacerbated by the use of materials like ruthenium that are unstable at higher temperatures.

Innovation Solution

A capping layer is selectively deposited on the sidewalls of conductive features to protect them from deformation during high-temperature processes, combined with the formation of air gaps between neighboring features to reduce capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If high-temperature processes are used to form conductive features, then thermal stability is improved, but material deformation increases

Engineering Contradiction:
Improvethermal stabilityVSAvoidsidewall deformation
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

A capping layer is deposited on the sidewalls of conductive features before high-temperature processes to prevent deformation. This preliminary protective action allows the subsequent thermal processing to occur without compromising sidewall integrity, resolving the contradiction between achieving thermal stability and maintaining manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If conductive features are formed with smaller dimensions to increase integration density, then device density is improved, but parasitic capacitance increases

Engineering Contradiction:
Improveintegration densityVSAvoidparasitic capacitance
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

Air gaps are introduced as intermediary spaces between neighboring conductive features. These air gaps act as electrical insulators that reduce parasitic capacitance between adjacent features, enabling higher integration density without the penalty of increased capacitive coupling.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If ruthenium material is used for conductive features, then electrical conductivity is improved, but thermal stability deteriorates

Engineering Contradiction:
Improveelectrical conductivityVSAvoidthermal stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The capping layer serves as a protective cushion deposited beforehand on the ruthenium conductive features. This layer shields the thermally unstable ruthenium material from direct exposure to high-temperature processes, preserving both the electrical conductivity benefits of ruthenium and the thermal stability required for manufacturing.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in conductive features with reduced resistance, improved thermal stability, and enhanced device density by minimizing sidewall deformation and parasitic capacitance, leading to improved reliability and yield.

Implementation Method 1

A capping layer is selectively deposited on the sidewalls of conductive features to protect them from deformation during high-temperature processes

Methodology Applied
Scientific EffectSelective deposition: Deposition (physical)

Implementation Method 2

combined with the formation of air gaps between neighboring features to reduce capacitance

Methodology Applied
Scientific EffectCapacitance reduction: Capacitance

Data Source

PatentUS20250323161A1Conductive features of semiconductor device and method of forming same
Publication Date: 2025.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250323161A1 patent drawing
  • US20250323161A1 patent drawing
  • US20250323161A1 patent drawing

AI summary

A method includes forming a conductive layer over a first dielectric layer; etching a recess in the conductive layer, wherein the recess exposes a top surface of the first dielectric layer; selectively depositing a capping layer on exposed sidewalls of the conductive layer within the recess; depositing a liner on the capping layer; forming a sacrificial material in the recess; and forming a second dielectric layer on the sacrificial material and on sidewalls of the recess; and after forming the second dielectric layer, performing a thermal process to remove the sacrificial material.