Stacked Microelectronic Packages With Sidewall Conductors
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Solution Overview
Problem
Conventional 3D microelectronic packaging methods, such as PoP technologies, face inefficiencies and complexities in interconnecting stacked microelectronic devices, particularly in reducing vertical connection needs and enhancing compactness and scalability.
Innovation Solution
A method for fabricating stacked microelectronic packages involves pre-singulated device panels with embedded microelectronic devices, where package sidewall conductors are formed over the panels before singulation, allowing for efficient electrical interconnection and reducing the need for vertical connections like BGAs, using flowable conductive materials and laser ablation for precise conductor formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional PoP packaging methods are used with vertical interconnection on package level, then microelectronic devices can be stacked in 3D arrangement, but the device complexity and manufacturing inefficiency increase due to numerous vertical connections like BGAs
Solution Approach 1:
The patent transitions interconnection from the vertical dimension (through-package BGAs) to the lateral dimension (sidewall conductors on package edges), reducing the number of vertical connections needed while maintaining 3D stacking benefits
Solution Approach 2:
The invention extracts and eliminates the need for complex vertical interconnection structures (BGAs, wire bonds) by using sidewall conductors that extend laterally from package edges, simplifying the overall interconnection architecture
2Reliability
If conventional PoP packaging with BGAs and wire bonding is used, then electrical interconnection between stacked devices is achieved, but manufacturing efficiency and productivity decrease
Solution Approach 1:
The patent merges the interconnection function into the package structure itself through sidewall conductors, eliminating separate interconnection steps (BGAs, wire bonding) and integrating electrical connection into the packaging process
Solution Approach 2:
Sidewall conductors are formed on package edges before stacking, allowing interconnection structures to be prepared in advance rather than requiring complex post-stack assembly operations
3Ease of manufacture
If conventional 2D packaging approach is used, then manufacturing processes are simpler, but the package compactness and device performance deteriorate due to longer interconnection lengths
Solution Approach 1:
The patent maintains manufacturing simplicity while achieving 3D compactness by using sidewall conductors that enable vertical stacking without the complexity of conventional 3D interconnection methods
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances manufacturing efficiency, cost-effectiveness, and productivity by enabling compact vertical device profiles and simplified manufacturing, while providing superior layer-to-layer interconnectivity compared to traditional methods.
Implementation Method 1
utilizing a laser to remove selected portions of the conductive material to define, at least in part, a plurality of sidewall conductors
Data Source
AI summary
Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package.