Stacked Microelectronic Packages With Sidewall Conductors
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Solution Overview
Problem
Conventional 3D microelectronic packaging technologies face challenges in reducing the vertical package profile and achieving efficient layer-to-layer interconnectivity, often relying on Ball Grid Arrays (BGAs) and through-package vias, which can be costly and less efficient.
Innovation Solution
The use of uniquely-formed sidewall conductors that eliminate or reduce the need for BGAs and through-package vias by providing electrically-conductive paths from the package topside to the bottom, enabling efficient interconnectivity between stacked microelectronic devices through a 'fill and drill' process involving flowable conductive materials and selective material removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D packaging technologies use BGAs and through-package vias for layer-to-layer interconnection, then reliable electrical connections are achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the need for BGAs and through-package vias by using sidewall conductors that extend vertically along the package edges to provide interlayer connections. This removes complex contact formations from the interior of the package while maintaining reliable electrical connections between stacked die layers.
Solution Approach 2:
The patent transitions from planar interconnection methods (BGAs on surfaces) to three-dimensional sidewall conductors that extend vertically along the package edges. This dimensional change allows electrical connections to be made through the side walls of the package rather than requiring through-vias or surface-mounted BGAs.
2Length of stationary object
If conventional packaging methods are used, then established manufacturing processes are maintained, but vertical package profile reduction is limited
Solution Approach 1:
The sidewall conductors are formed during the packaging process before final assembly, allowing subsequent stacking and connection operations to proceed more efficiently. The conductors are prepared in advance on the package substrate, enabling direct connection to die edges without requiring additional through-package via formation steps.
3Ease of manufacture
If sidewall conductors are used to eliminate BGAs, then manufacturing cost is reduced, but new fabrication processes are required
Solution Approach 1:
The patent combines the formation of sidewall conductors with existing package substrate fabrication processes. The conductors are integrated into the substrate structure during normal manufacturing operations, merging multiple functions (substrate formation, conductor creation, and interconnection provision) into a unified process flow that reduces overall manufacturing complexity despite the novel approach.
Data Source
AI summary
Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.