Stacked Microelectronic Packages With Sidewall Conductors
Solution Overview
Problem
Traditional microelectronic packaging methods are limited by their two-dimensional approach, which results in bulky devices with longer interconnection lengths, leading to signal delays, and require the use of Ball Grid Arrays (BGAs) or through-package vias for interconnecting stacked microelectronic devices.
Innovation Solution
The use of uniquely formed sidewall conductors that eliminate or reduce the need for BGAs and through-package vias by providing electrically conductive paths between package layers and microelectronic devices, allowing for vertical interconnections and reducing the vertical package profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional two-dimensional packaging methods are used, then manufacturing processes are simpler, but the package size becomes bulky and interconnection length increases leading to signal delays
Solution Approach 1:
The patent transitions from traditional two-dimensional packaging to three-dimensional stacked packaging, where multiple microelectronic devices are arranged vertically in stacked layers and interconnected through the package body. This dimensional change reduces the lateral footprint and overall package volume while maintaining all necessary interconnections, directly addressing the contradiction between compact size and manufacturing complexity.
2Reliability
If stacked microelectronic devices are interconnected using BGAs or through-package vias, then vertical interconnections are achieved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent extracts and eliminates the need for complex BGAs (Ball Grid Arrays) and through-package vias from the interconnection system. Instead, it uses simplified conductive paths formed within the package body that directly connect corresponding pads on stacked devices, removing the problematic intermediate elements that caused manufacturing complexity while maintaining reliable vertical interconnections.
Solution Approach 2:
The patent introduces a simplified conductive path structure as an intermediary element within the package body that facilitates direct electrical connection between corresponding pads on stacked microelectronic devices. This mediator replaces the complex BGA and via structures, providing reliable interconnection through a manufacturable approach using standard packaging processes.
3Loss of time
If vertical interconnections are implemented through the package body, then interconnection length is reduced and signal delay decreases, but the package structure becomes more complex
Solution Approach 1:
The patent implements vertical interconnections by stacking devices in the third dimension and routing conductive paths through the package body in the vertical direction. This approach minimizes the length of interconnection paths compared to lateral routing in two-dimensional packaging, thereby reducing signal delay and transmission loss while the conductive path structure integrates seamlessly with the stacked device architecture.
4Ease of manufacture
If sidewall conductors are used for interconnection, then manufacturing complexity is reduced and signal delay decreases, but sidewall conductors are vulnerable to damage during processing and transport
Solution Approach 1:
The patent applies a protective coating or encapsulation layer over the sidewall conductors before and during subsequent processing steps and transport. This protective measure is implemented in advance to prevent mechanical damage, oxidation, or contamination of the exposed sidewall conductor surfaces, thereby maintaining their electrical integrity and reliability while preserving the manufacturing advantages of the sidewall conductor approach.
Data Source
AI summary
A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall. A cavity is formed on an external surface of the package body between a first one of the package edge conductors and a second one of the package edge conductors. Electrically conductive material is in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package.