Sidewall Gate Electrode Height Optimization for Ion Penetration
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Solution Overview
Problem
The challenge in device scaling of self-align split gate type memory cells is due to the insufficient height of the side wall gate electrode, leading to ion implantation issues and threshold voltage fluctuations, particularly evident in the 90-nm design rule where the gate height is insufficient to prevent ion penetration into the channel.
Innovation Solution
The solution involves forming the gate electrode structure with a height equal to or greater than the sum of the required height to prevent ion penetration and the height of the adjacent structure, allowing for the use of a thin photoresist film, and then selectively reducing the gate electrode height in the logic area using methods like multilayer structures or conductive and dielectric film combinations to optimize both memory cell and logic area performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the side wall gate electrode height is reduced to enable device scaling, then device integration density is improved, but ion implantation control deteriorates and threshold voltage fluctuates
Solution Approach 1:
The gate electrode is segmented into two distinct parts: a first gate electrode for the memory cell area and a second gate electrode for the logic circuit area. This segmentation allows each gate to be independently optimized - the first gate can be taller to prevent ion penetration in the memory cell, while the second gate can be shorter to enable fine patterning in the logic circuit area using thin photoresist films.
Solution Approach 2:
Different gate electrode heights are implemented in different spatial locations on the semiconductor substrate. The memory cell area receives a taller gate electrode structure to ensure proper ion implantation blocking, while the logic circuit area receives a shorter gate electrode to facilitate advanced photolithography patterning. This local differentiation resolves the contradiction between device scaling and ion implantation control.
2Ease of manufacture
If a uniform gate electrode height is used across memory and logic areas, then manufacturing simplicity is maintained, but performance optimization for both areas cannot be achieved
Solution Approach 1:
The gate electrode structure is divided into separate first and second gate electrodes that can be formed with different heights. This segmentation enables independent optimization of the memory cell region (with taller gates for ion blocking) and logic circuit region (with shorter gates for fine patterning), achieving performance optimization for both areas while maintaining a relatively simple manufacturing process using standard photolithography and etching techniques.
Data Source
AI summary
A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.