Sidewall SONOS Memory Device L-Shaped Charge Trapping

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Solution Overview

Problem

Sidewall SONOS transistors face issues with electron drift, leading to charge density degradation and data retention problems, and are not scalable to sub-0.130 μm semiconductor manufacturing technologies due to limitations in silicon oxide spacer manufacturing and reproducibility of L-shaped charge trapping material formations.

Innovation Solution

A method involving the formation of an oxide-nitride-oxide structure with a L-shaped cross-section, where a silicon nitride spacer is deposited and separated from the oxide-nitride-oxide stack by a top oxide material, reducing electron drift and enhancing charge density retention, and allowing scalability to sub-0.130 μm technology generations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a conventional sidewall SONOS transistor structure is used, then two bits per transistor can be stored, but electron drift occurs leading to charge density degradation and data retention problems

Engineering Contradiction:

Improvecharge storage capacityVSAvoidcharge density retention

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The charge trapping layer is segmented into multiple discrete regions (first charge trapping layer and second charge trapping layer) separated by an insulating layer. This segmentation isolates charge storage regions, preventing electron drift between adjacent regions while maintaining two-bit storage capability. Each segmented region can independently retain charge without interference from neighboring regions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

An insulating layer is introduced as an intermediary between the first and second charge trapping layers. This intermediary layer acts as a barrier that prevents electron drift from one charge trapping region to another, thereby protecting charge density retention while allowing both layers to function as storage regions for two-bit data.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If silicon oxide spacers are used in sidewall SONOS transistors, then manufacturing is feasible, but scalability to sub-0.130 μm semiconductor manufacturing technologies is prevented

Engineering Contradiction:

Improvespacer manufacturabilityVSAvoidtechnology node scalability

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The material parameter of the spacer is changed from silicon oxide to mandrel material (such as silicon nitride or polysilicon). This parameter change enables the spacer to be manufactured using existing processes while also being compatible with sub-0.130 μm technology nodes, as mandrel materials can be precisely patterned at smaller dimensions using standard semiconductor fabrication techniques.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7482236B2Structure and method for a sidewall SONOS memory device

Publication Date: 2009.01.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A gate stack is formed on a substrate. The gate stack has a sidewall. An oxide-nitride-oxide material is deposited on the gate stack. Portions of the oxide-nitride-oxide material are removed to form an oxide-nitride-oxide structure. The oxide-nitride-oxide structure has a generally L-shaped cross-section with a vertical portion along at least part of the gate stack sidewall and a horizontal portion along the substrate. A top oxide material is deposited over the substrate. A silicon nitride spacer material is deposited over the top oxide material. Portions of the top oxide material and the silicon nitride spacer material are removed to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material. Source/drain regions are formed in the substrate.