Sieve-like Etch Stop Layer for Semiconductor Via Patterning

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Solution Overview

Problem

As semiconductor devices shrink in size, patterning techniques become increasingly challenging due to the need for precise integration of conductive and insulating materials, leading to issues with critical dimension control and the formation of undesired conductive structures between interconnects.

Innovation Solution

The use of a novel method involving a sieve-like etch stop layer made of AlON, which allows for self-aligned via patterning and growth of conductive material through it, preventing the formation of spike-shaped or tiger-tooth conductive material and maintaining electrical connections between conductive lines and vias without additional etching steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional patterning techniques are used with shrinking feature sizes, then integration density is improved, but critical dimension control deteriorates and undesired conductive structures form

Engineering Contradiction:
Improveintegration densityVSAvoidcritical dimension control
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

A sieve-like etch stop layer is introduced as an intermediary structure between the insulating material layer and the conductive material. This etch stop layer with controlled porosity (20-80% open area) acts as a mediator that allows precise control of conductive material growth while preventing undesired lateral expansion, thereby maintaining critical dimension control as integration density increases

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs a porous etch stop layer with specifically controlled porosity (20-80% open area) to enable selective growth of conductive material. The porous structure allows vertical growth while blocking lateral expansion, solving the critical dimension control problem that arises when scaling to higher integration densities

Inventive Principle:
Principle #31Porous materials

2Manufacturing precision

If additional etching steps are added to prevent spike-shaped conductive material, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvevia dimension controlVSAvoidprocess steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The sieve-like etch stop layer is prepared in advance with its specific porous structure before conductive material deposition. This preliminary preparation of the etch stop layer creates self-aligned patterns that guide conductive material growth, eliminating the need for subsequent etching steps to correct spike-shaped formations and thereby reducing overall process complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The porous etch stop layer provides self-aligned via patterning functionality, where the structure itself serves as the pattern definition for conductive material growth. This self-service mechanism eliminates the need for additional etching steps and complex alignment processes, maintaining manufacturing precision while reducing device complexity

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach achieves precise via dimensions, avoids critical dimension enlargement, and maintains low resistance properties, reducing the risk of time-dependent dielectric breakdown and simplifying the manufacturing process by allowing simultaneous removal of etch masks.

Implementation Method 1

A region of the etch stop layer beneath the via includes a material of the via, indicating that the conductive material grew through the porous etch stop layer via diffusion

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS9293413B2Semiconductor devices and methods of manufacture thereof
Publication Date: 2016.03.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9293413B2 patent drawing
  • US9293413B2 patent drawing
  • US9293413B2 patent drawing

AI summary

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an insulating material layer over a workpiece, patterning an upper portion of the insulating material layer with a conductive line pattern, and forming a stop layer comprising a metal oxide or a metal nitride over the patterned insulating material layer. A masking material is formed over the stop layer, and the masking material is patterned with a via pattern. The via pattern of the masking material is transferred to a lower portion of the insulating material layer.