SiGe Thin Film Surface Roughness Reduction via CMP

Solution Overview

Problem

Silicon germanium (SiGe) thin films deposited using LPCVD or PECVD often exhibit surface roughness, which leads to photolithography defects, increased etch times, and current leakage in memory devices, posing challenges for the miniaturization and performance of semiconductor chips.

Innovation Solution

The application of chemical mechanical planarization (CMP) to smooth the SiGe thin films, followed by post-CMP cleaning, significantly reduces surface roughness, thereby improving the integrity of underlying CMOS devices and reducing defects and leakage issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LPCVD or PECVD is used to deposit SiGe thin films, then the films can be formed at lower temperatures suitable for CMOS devices, but the films exhibit surface roughness leading to photolithography defects and current leakage

Engineering Contradiction:
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

A buffer layer is deposited prior to the SiGe thin film to prepare the substrate surface, and a capping layer is deposited after the SiGe film to protect and smooth the surface. These preliminary and subsequent layers prevent surface roughness development while maintaining the low-temperature deposition advantage

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses a composite structure consisting of multiple materials: buffer layer material, SiGe thin film material, and capping layer material. This composite approach allows each layer to perform its specific function, with the buffer and capping layers compensating for the surface roughness issue in the SiGe film

Inventive Principle:
Principle #40Composite materials

2Productivity

If conventional deposition processes are used, then SiGe films can be deposited, but surface roughness increases leading to increased etch times and photolithography defects

Engineering Contradiction:
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The buffer layer is deposited in advance to create a foundation that enables faster deposition of the SiGe film without subsequent surface roughness issues. The capping layer is applied immediately after to maintain surface smoothness, thereby reducing the need for extended etching processes

Inventive Principle:
Principle #10Preliminary action

3Reliability

If surface roughness is reduced through additional processing steps, then photolithography defects and current leakage are minimized, but process complexity increases

Engineering Contradiction:
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The buffer layer deposition, SiGe film deposition, and capping layer deposition are merged into a single continuous low-temperature deposition process. This integration achieves surface roughness reduction without requiring separate complex processing steps, maintaining device integrity while limiting process complexity

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The process achieves a surface roughness reduction of 50-100% without substantial thickness compromise, leading to improved fabrication of memory devices with reduced defects and enhanced performance by minimizing CD variations and current leakage.

Implementation Method 1

performing a chemical mechanical planarization (CMP) process to the jagged surface of the SiGe material

Methodology Applied
Scientific EffectChemical mechanical planarization:

Implementation Method 2

depositing a silicon germanium (SiGe) material upon a surface of a substrate to form a SiGe material film

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS9425046B1Method for surface roughness reduction after silicon germanium thin film deposition
Publication Date: 2016.08.23
  • US9425046B1 patent drawing
  • US9425046B1 patent drawing
  • US9425046B1 patent drawing

AI summary

Techniques for processing silicon germanium (SiGe) thin films to reduce surface roughness thereof are provided herein. In an aspect, a method is disclosed that includes depositing a silicon germanium (SiGe) material upon a surface of a substrate at or below about 450 degrees Celsius, the substrate having a plurality of CMOS devices therein and forming, from the deposited SiGe material, a SiGe material film, wherein the SiGe material film has a jagged surface comprising projections and indentations extended along a direction substantially perpendicular to the surface of the substrate. The method further includes performing a chemical mechanical planarization (CMP) process to the jagged surface of the SiGe material, and reducing variations between the projections and the indentions along the direction substantially perpendicular to the surface of the substrate, and transforming the jagged surface of the SiGe material into a relatively smooth surface, compared to the jagged surface.