SiGe FinFET Strain Engineering via Ge Diffusion
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Solution Overview
Problem
The formation of silicon germanium (SiGe) fins in fin-type field-effect transistors (FinFETs) is challenging due to the small volume available for strain engineering, leading to high costs and reduced hole mobility, as existing methods like epitaxial growth require high-temperature thermal anneal processes that relax compressive stress.
Innovation Solution
A method involving the conformal deposition of an amorphous or polycrystalline SiGe thin film on semiconductor fins, followed by oxidation to diffuse germanium into the fins, and subsequent removal of the oxidized portion, which controls germanium concentration and strain, reducing production costs and enhancing mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional epitaxial growth methods are used to form SiGe fins, then fins can be created, but high-temperature thermal anneal processes are required that relax compressive stress and increase production costs
Solution Approach 1:
The patent changes the temperature parameter of the deposition process from high-temperature epitaxial growth to low-temperature atomic layer deposition (ALD), enabling SiGe fin formation without thermal annealing that would relax compressive stress
Solution Approach 2:
The patent replaces the thermal field (heat-based epitaxial growth) with a chemical field (low-temperature ALD process), eliminating the need for high-temperature thermal anneal while maintaining compressive stress in the SiGe fins
2Length of moving object
If fin geometries are reduced to 10 nanometer device designs, then device scaling is achieved, but fabrication of SiGe fins becomes expensive and difficult
Solution Approach 1:
The patent replaces conventional high-temperature epitaxial growth with low-temperature atomic layer deposition (ALD), enabling precise control of SiGe fin fabrication at 10 nanometer scale with reduced process complexity and cost
Solution Approach 2:
The patent changes the deposition temperature parameter to low-temperature ALD conditions, which enables better control over thin film formation at nanometer scales while simplifying the fabrication process
3Volume of moving object
If the volume of the fin is small, then FinFET structure is achieved, but strain engineering becomes difficult and hole mobility is reduced
Solution Approach 1:
The patent changes the deposition temperature to low-temperature ALD conditions, which preserves compressive stress in the small-volume SiGe fins and maintains high hole mobility despite the reduced fin volume
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher performance FinFETs with controlled germanium distribution and strain, reducing production costs and improving carrier mobility compared to conventional epitaxial growth methods.
Implementation Method 1
oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin
Implementation Method 2
conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin
Data Source
AI summary
A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.