Silicon Germanium Shell Channel Fabrication on Bulk Silicon
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Solution Overview
Problem
Current methods for fabricating p-channel MOSFETs using silicon germanium materials are complex and difficult to integrate with conventional silicon CMOS processes, and they struggle to form a thin, uniform channel layer on silicon wires, leading to reduced gate controllability and increased process costs.
Innovation Solution
A method involving the alternated stacking of silicon germanium and silicon layers on a semiconductor substrate, followed by sequential formation of insulating layers and patterning to create channel fine patterns, source and drain patterns, and a silicon germanium shell, allowing for the fabrication of a semiconductor device with a silicon germanium shell channel using a conventional silicon CMOS process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to form silicon germanium channel layers on silicon wires, then the channel layer can be formed, but the process becomes complicated and difficult to integrate with conventional silicon CMOS processes
Solution Approach 1:
The patent uses alternating stacking of silicon germanium layers and silicon layers to create a homogeneous structure that is compatible with conventional silicon CMOS processes. The silicon layers serve as sacrificial layers that can be selectively removed, while the silicon germanium layers form the desired channel structure, enabling integration with standard silicon fabrication processes.
Solution Approach 2:
The channel structure is segmented into alternating silicon germanium and silicon layers. This segmentation allows for selective processing where silicon layers can be removed to create suspended or released structures, while silicon germanium layers remain to form the functional channel, simplifying the overall fabrication process.
2Length of moving object
If thin silicon germanium channel layers are formed on silicon wires, then the channel layer thickness is reduced, but the uniformity and gate controllability deteriorate
Solution Approach 1:
The alternating stacking of silicon germanium and silicon layers ensures uniform thickness and composition throughout the structure. Each layer is deposited with controlled thickness, and the periodic structure maintains homogeneity, enabling precise control over channel dimensions and improved gate controllability.
Solution Approach 2:
The silicon layers are deposited as sacrificial layers in advance, allowing for subsequent selective removal to create the final channel structure. This preliminary action enables precise thickness control of the silicon germanium channel layers while maintaining uniformity throughout the device.
3Reliability
If silicon germanium channel structures are fabricated using non-conventional methods, then the channel structure can be formed, but the process cost increases
Solution Approach 1:
The alternating silicon germanium-silicon layer structure serves multiple functions: it provides the silicon germanium channel for device operation, uses silicon layers as sacrificial elements for structure release, and maintains compatibility with conventional silicon CMOS fabrication processes. This multi-functionality reduces the need for specialized processes and equipment, thereby lowering manufacturing costs.
Solution Approach 2:
The patent utilizes parameter changes in the deposition process to control the thickness and composition of alternating layers. By adjusting deposition parameters such as temperature, pressure, and gas flow rates, the process achieves precise control over layer properties while using standard silicon fabrication equipment, reducing overall process costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the fabrication of semiconductor devices with a uniform silicon germanium shell channel on bulk silicon substrates, improving device performance and reducing process complexity and costs by utilizing a conventional silicon CMOS process.
Implementation Method 1
forming an active layer by alternately stacking a silicon germanium layer and a silicon layer on a semiconductor substrate
Implementation Method 2
forming a plurality of channel fine patterns by removing both ends of the sidewall insulating layer exposed by removing the dummy patterns
Data Source
AI summary
A method for fabricating a semiconductor device is carried out so that silicon nanowires may be made of vertically stacked one or more floating silicon layers, and a silicon buffer layer may be surrounded on each surface of the silicon nanowires with a sufficient thickness, e.g., close to the diameter of the nanowire, and then a silicon germanium shell may be formed on it. Thus, a semiconductor device having a silicon germanium shell channel structure can be fabricated with a uniform thickness even on a bulk silicon substrate using a conventional silicon CMOS process.