Sigma-Delta Reference Clock Modulation for Fractional PLL Synthesis
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Solution Overview
Problem
Existing fractional-N frequency synthesis methods require additional hardware, increasing cost, power consumption, and design complexity, particularly in systems like high-speed optical transceivers, due to the need for dedicated fractional PLLs and analog solutions.
Innovation Solution
A digital circuit using a programmable frequency divider controlled by a Sigma-Delta modulator and an integer-N PLL achieves fractional-N frequency synthesis by modulating the reference clock, eliminating the need for a dedicated fractional PLL and utilizing existing PLLs to realize a Numerically Controlled Oscillator (NCO) function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dedicated fractional-N PLL is used to achieve fractional frequency synthesis, then frequency resolution is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent combines the fractional-N frequency synthesis function with an existing integer-N PLL by inserting a sigma-delta modulator in the feedback path. This merging eliminates the need for a separate dedicated fractional PLL, reducing device complexity while maintaining frequency resolution through the modulator's ability to generate fractional division ratios.
Solution Approach 2:
The existing integer-N PLL is made universal by enabling it to perform both integer and fractional frequency synthesis functions. The sigma-delta modulator allows the same PLL circuit to operate in different modes (integer or fractional) based on the feedback division ratio, eliminating the need for dedicated hardware for each function.
2Adaptability or versatility
If a dedicated fractional-N PLL is used to achieve fractional frequency synthesis, then frequency synthesis capability is improved, but power consumption increases
Solution Approach 1:
The patent merges the fractional frequency synthesis capability into the existing PLL power domain. By using the same VCO and phase detector for both integer and fractional modes, the system avoids duplicating power-consuming components, reducing overall power consumption while maintaining full frequency synthesis capability.
Solution Approach 2:
The sigma-delta modulator in the feedback path enables the existing PLL to self-adapt to fractional frequency synthesis without requiring additional active components. The modulator dynamically adjusts the feedback division ratio to achieve fractional frequencies using the same hardware resources already present in the integer-N PLL.
3Adaptability or versatility
If an integer-N synthesizer is redesigned to convert it to a fractional-N synthesizer, then fractional frequency capability is improved, but design effort increases
Solution Approach 1:
The patent extracts the fractional-N functionality from the complex feedback path of a traditional fractional PLL and implements it through a simpler sigma-delta modulator inserted in the feedback path of an existing integer-N PLL. This extraction approach maintains the core integer-N PLL architecture while adding minimal circuitry to achieve fractional capability.
Solution Approach 2:
Instead of redesigning the entire PLL architecture to support fractional frequencies from the ground up, the patent inverts the approach by taking an existing integer-N PLL and adding a sigma-delta modulator to the feedback path. This inversion allows fractional capability to be achieved through a minor modification rather than a complete redesign.
4Measurement precision
If a fully dedicated fractional PLL is used to serve as reference clock for another PLL, then frequency accuracy is improved, but chip footprint increases
Solution Approach 1:
The patent merges the reference clock generation function with the existing PLL by using the same VCO and feedback path. The sigma-delta modulator enables the same hardware to serve dual purposes: generating accurate reference clocks and providing fractional frequency synthesis, thereby eliminating the need for additional dedicated PLL circuits and reducing chip footprint.
Data Source
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AI summary
A circuit (30) includes a programmable frequency divider (14) which receives a high-speed clock (12), ƒin, as an input and which provides a modulated reference clock (20) as an output; a Sigma-Delta modulator (16) which receives a Frequency Control Word (FCW) (18) and which is connected to the programmable frequency divider (14) to receive the modulated reference clock (20) as a sample clock and to control an average frequency of the modulated reference clock (20); and an integer-N Phase Lock Loop (PLL) (22) which receives the modulated reference clock (20) and outputs a clock output..