Sigma-Delta Time Converter for Low-Noise ADPLL Phase Locking
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Solution Overview
Problem
Existing digital time converters, particularly those used in all-digital phase-locked loops, face limitations in accuracy due to propagation time constraints and require additional processing for normalization, while also needing multiple stages with calibration and additional clock signals.
Innovation Solution
A sigma-delta type digital-to-time converter that integrates pulses representing time intervals, centers the conversion zero at the midpoint of the dynamic range, and implements negative sigma-delta feedback, allowing for single-bit quantization and integration without additional clock signals, utilizing existing low-pass filters in the phase-locked loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a flash time-digital converter with delay line stages is used, then time interval measurement is achieved, but measurement precision is limited by propagation time of each stage and requires calibration
Solution Approach 1:
The patent replaces the traditional flash converter architecture with a sigma-delta modulator architecture that uses sequential integration and feedback instead of parallel delay line stages. This substitution eliminates the need for propagation delay calibration while achieving high measurement precision through noise shaping and oversampling techniques.
Solution Approach 2:
The patent changes the fundamental operating parameters by using a single integrator with dynamic range modulation instead of multiple fixed-delay stages. The conversion zero is positioned at the midpoint of the dynamic range, and the system uses feedback control to adjust integration results, transforming the measurement approach from direct sampling to iterative refinement.
2Measurement precision
If normalization processing is applied to converter output in ADPLL, then output accuracy is improved, but device complexity increases due to additional processing
Solution Approach 1:
The patent creates an equipotential operating point by positioning the conversion zero at the midpoint of the integrator's dynamic range. This centering technique ensures maximum utilization of the integrator's range and eliminates the need for additional normalization processing, as the output is already optimized for ADPLL operation.
Solution Approach 2:
The sigma-delta modulator performs self-normalization through its feedback mechanism. The quantization feedback automatically adjusts the integration result to maintain the conversion zero at the optimal point, eliminating the need for external normalization circuits or processing stages.
3Measurement precision
If multiple clock signals are used in digital time converter, then timing control is improved, but device complexity increases
Solution Approach 1:
The patent makes the single clock signal universal by using it for multiple functions: triggering the integrator, generating the feedback signal, and timing the quantization process. This multi-functionality eliminates the need for multiple dedicated clock signals while maintaining precise timing control throughout the conversion process.
Solution Approach 2:
The patent merges multiple clock signal functions into a single clock source. The same clock that triggers the integrator also generates the feedback timing and synchronizes the quantization, combining what would traditionally require separate clock domains into one unified timing reference.
4Measurement precision
If quantization noise is present in time-digital converter, then measurement resolution is affected, but filtering complexity increases to reduce noise density
Solution Approach 1:
The patent uses periodic feedback action at the clock frequency to shape the quantization noise spectrum. The sigma-delta modulator's periodic feedback creates noise shaping that pushes quantization noise to higher frequencies, allowing simple low-pass filtering in the ADPLL to effectively reduce noise density in the measurement band.
Solution Approach 2:
The patent employs feedback to actively manage quantization noise. The quantization result is fed back to the integrator, creating a closed-loop system that shapes the noise spectrum. This feedback mechanism reduces in-band quantization noise without requiring complex filtering, as the noise is naturally pushed out of the measurement bandwidth.
Data Source
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AI summary
The present description relates to a converter comprising: a circuit (C1) providing a first pulse (P1) determined by a difference between an active edge of a first signal (S1) and an active edge of a second signal (S2); a circuit (INT) which, at each first pulse (P1), integrates the first pulse (P1), a second pulse (P2) starting after the first pulse (P1) in synchronism with a clock signal (clk), and a third pulse (P3) starting after the third pulse (P3) in synchronism with the clock signal (clk); a circuit (C3) sampling on one bit (OUT1) an output signal (RES1) of the integrator circuit (INT) at the beginning of each third pulse (P3); and two circuits (C2, C4) generating, for each first pulse (P1), respectively the corresponding second pulse and the corresponding third pulse from the first bit (OUT1).