Transmitting and Receiving Circuit for Signal Level and Impedance Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor test devices face challenges in efficiently converting signal levels and impedance between the test device and the test target device, leading to potential operational instability and incompatibility due to differing signal levels and impedances.
Innovation Solution
The transmitting and receiving circuit incorporates a first CMOS inverter, calculation amplifiers, resistors, level shifters, and hysteresis comparators to convert signal levels and impedance, ensuring compatibility between the test device and test target device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If signal level conversion is performed between test device and test target device, then compatibility between devices is improved, but circuit complexity increases due to multiple conversion stages
Solution Approach 1:
The signal level conversion is divided into multiple stages: first CMOS inverter for initial level conversion, then calculation amplifier for precise level adjustment, and finally hysteresis comparator for receiving side conversion. Each stage handles a specific portion of the conversion task, making the overall complex conversion process manageable and modular.
Solution Approach 2:
The calculation amplifier acts as an intermediary component between the CMOS inverter and the rest of the circuit. It receives the converted signal from the inverter and further processes it to achieve the target signal level, serving as a mediator that bridges different signal level domains.
2Reliability
If impedance matching is implemented between test device and test target device, then signal transmission stability is improved, but device complexity increases
Solution Approach 1:
The circuit combines multiple functions into integrated components. The CMOS inverter simultaneously performs signal inversion and initial level conversion, while the calculation amplifier combines buffering, level adjustment, and impedance transformation functions. This merging reduces the number of separate components needed.
Solution Approach 2:
The calculation amplifier serves multiple purposes: it buffers the signal from the CMOS inverter, adjusts the signal level to the target value, and provides impedance transformation. This multi-functionality reduces the need for separate dedicated components for each function.
3Manufacturing precision
If multiple conversion stages are used for signal level adjustment, then signal level precision is improved, but operational stability deteriorates due to potential oscillation
Solution Approach 1:
The hysteresis comparator introduces feedback mechanisms that provide stable operating points. The hysteresis effect creates different threshold levels for rising and falling edges, preventing the circuit from oscillating around a single threshold and ensuring stable switching behavior even with multiple conversion stages.
Solution Approach 2:
The calculation amplifier is designed with proper biasing and gain control to prevent signal saturation or oscillation before it occurs. By pre-configuring the amplifier's operating parameters, the circuit avoids instability issues that could arise during signal conversion.
Data Source
AI summary
A transmitting and receiving circuit may include a first CMOS inverter configured to receive a first power supply signal and a first input signal. The transmitting and receiving circuit may include a first calculation amplifier including a non-inverted input terminal connected to an output terminal of the first CMOS inverter, and a first resistor connected between the output terminal of the first calculation amplifier and a first node. The output terminal of the first calculation amplifier and an inverted input terminal of the first calculation amplifier may be connected to each other. A first output signal may have a level smaller than that of the first input signal and may be output to the first node.