High-Speed Signaling Error Interrupt Logic with Time-Window Counting
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Solution Overview
Problem
Conventional communication systems experience increased latency and reduced performance due to excessive interrupts caused by frame error rate thresholds being exceeded, leading to inaccurate error detection and processing delays.
Innovation Solution
Implementing interrupt logic in the receiver that raises interrupts only when a programmable number of errors is detected within a specified period, allowing for two threshold levels: a soft interrupt for preparatory actions and a hard interrupt for link shutdown, thereby reducing processing times and improving system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the receiver transmits an interrupt whenever a threshold number of errors is satisfied, then error detection sensitivity is improved, but interrupt frequency increases causing increased latency and performance reduction
Solution Approach 1:
The patent implements a time-window based error counting mechanism where errors are accumulated only within specific time periods. The receiver counts errors occurring within a defined time window and generates interrupts only when the error count within that window exceeds a threshold. This periodic evaluation approach filters out transient error spikes while maintaining sensitivity to sustained error conditions, thereby reducing unnecessary interrupts and improving system performance without sacrificing error detection capability
Solution Approach 2:
The patent introduces dynamic parameters including programmable time windows and adjustable error thresholds that can be configured based on link conditions. The system can adapt the time window duration and error threshold values to match different operational scenarios, allowing optimal balance between error detection sensitivity and interrupt frequency. This dynamic configuration enables the system to respond appropriately to varying error patterns while maintaining high productivity
2Measurement precision
If the receiver transmits excessive interrupts when error thresholds are exceeded, then error detection accuracy is improved, but latency increases due to processing delays
Solution Approach 1:
The patent implements preliminary error accumulation within time windows before triggering interrupts. Rather than immediately responding to each threshold exceedance, the system预先 accumulates errors within defined time periods and only generates interrupts after confirming sustained error conditions. This preliminary evaluation phase filters out transient errors and prevents premature interrupt generation, reducing latency while maintaining accurate error detection of genuine link problems
3Device complexity
If conventional error threshold interrupt mechanisms are used, then error monitoring is simplified, but excessive interrupts cause increased processing overhead
Solution Approach 1:
The patent maintains relatively simple error monitoring logic by using periodic time-window based evaluation. The receiver counts errors within fixed time windows and compares against thresholds, which is conceptually similar to conventional mechanisms. However, the periodic time-window structure inherently filters out transient error spikes, reducing the number of interrupts generated and thereby decreasing processing overhead without significantly increasing monitoring complexity
Solution Approach 2:
The patent accumulates errors within time windows before triggering interrupts, which represents a form of partial action. Instead of responding to every single error threshold exceedance, the system waits for sustained error conditions within the time window. This partial accumulation approach reduces the frequency of interrupt generation and associated processing overhead while still providing timely notification of genuine error conditions
Data Source
AI summary
A receiver device includes detection logic, error counter logic, and threshold logic. The detection detects frame errors in data frames received by a transmitter device. The error counter logic increments a first value of an error count responsive to each error signal, indicative of a frame error in a data frame, received from the detection logic. The error counter logic reduces the first value to a second value (non-zero value) for the error count responsive to receiving a decrement signal and a period marker signal corresponding to a programmable period. The error counter logic resets the first value or the second value of the error count to zero responsive to receiving a reset signal. The threshold logic compares a current value of the error count with a threshold number of frame errors and output an interrupt responsive to the current value satisfying the threshold number of frame errors.