Semiconductor Silicide Layer Sidewall Formation
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Solution Overview
Problem
In semiconductor devices, the silicide layer formed on the active region does not effectively reduce transistor serial resistance due to the lack of active area between the contact landing area and the transistor gate spacer, necessitating a method to minimize this resistance.
Innovation Solution
A semiconductor structure and manufacturing method involving a semiconductor substrate with protrusions and blocks, where a dielectric layer is deposited, and a silicide layer is formed on the sidewalls and upper surface of the substrate through a thermal process, reducing transistor serial resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicide layer is formed on the active region, then the transistor serial resistance should be reduced, but the silicide layer does not effectively reduce resistance when there is no active area between the contact landing area and the transistor gate spacer
Solution Approach 1:
The invention transitions from forming silicide only on the horizontal upper surface to forming silicide on both vertical sidewalls and the upper surface, utilizing the third dimension (vertical dimension) to create additional conductive pathways that reduce serial resistance even when horizontal active area is minimal
Solution Approach 2:
The silicide structure is formed within and around the protrusion geometry, with the liner and metal layer nested within the protrusion sidewalls, creating a three-dimensional silicide region that extends vertically along the sidewalls and horizontally on the upper surface
2Reliability
If the metal layer thickness is increased to ensure complete coverage, then the silicide layer thickness increases, but excessive thickness may cause processing issues and increased resistance
Solution Approach 1:
The invention optimizes the metal layer thickness parameter to be greater than 50nm but less than 100nm, and controls the liner thickness to be greater than 1nm but less than 5nm, creating a balance between ensuring complete coverage and maintaining manufacturability and electrical performance
Solution Approach 2:
The metal layer is applied with intentional excess thickness to ensure complete coverage of the protrusion sidewalls and upper surface, then the unreacted portion is removed through etch-back, ensuring full coverage while controlling final thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described method effectively reduces transistor serial resistance by forming a silicide layer with controlled thickness and crystal phase over specific substrate regions, enhancing the semiconductor device's performance.
Implementation Method 1
performing a thermal process to at least make a portion of the metal layer react with the liner and the semiconductor substrate to form a silicide layer
Implementation Method 2
performing a wet etch process to remove an unreacted portion of the metal layer over a front surface of the dielectric layer
Data Source
AI summary
The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a dielectric layer, and silicide layer. The semiconductor substrate has a plurality of protrusions. The dielectric layer is disposed over the semiconductor substrate and has a plurality of blocks disposed over the protrusions. The silicide layer is disposed over a first sidewall of the protrusions, a second sidewall of the blocks, and an upper surface of the semiconductor substrate adjacent to the first sidewall, and a bottom surface of the silicide layer is lower than a first surface of the semiconductor substrate. The present disclosure further provides a method for manufacturing the semiconductor structure.