Silicide Pass-Through Contact for MOL Congestion
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Solution Overview
Problem
The congestion of middle-of-line (MOL) and back-end-of-line (BEOL) layers in semiconductor devices, particularly in advanced technology nodes, leads to spacing issues and compromises in design rules such as M1 to gate contact spacing, resulting in manufacturing challenges and reliability risks.
Innovation Solution
A method involving the formation of a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains, which extends from one raised source/drain to the other and below the gate contact, using materials like tungsten, copper, or titanium silicide, to reduce congestion without compromising design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard pass-through contact structures are used in advanced technology nodes, then device density is improved, but MOL and BEOL layer congestion occurs
Solution Approach 1:
The patent introduces a vertical pass-through contact structure that extends through the gate contact layer into the substrate, utilizing the vertical dimension to establish electrical connections. This eliminates the need for lateral routing through congested MOL and BEOL layers, thereby reducing layer congestion while maintaining high device density.
Solution Approach 2:
The patent employs an intermediary contact structure that passes through the gate contact layer, serving as a mediator to establish electrical connections between source/drain regions without requiring additional MOL or BEOL routing. This intermediary path resolves the congestion issue by providing a direct vertical connection route.
2Area of moving object
If M1 to gate contact spacing is reduced to 40 nm, then cell area is reduced, but lateral flipping and M1 jogs are required causing corner rounding and congestion
Solution Approach 1:
The patent transitions from lateral M1 routing to vertical pass-through contacts, eliminating the need for M1 jogs and lateral flipping. The vertical dimension provides a direct path that avoids corner rounding issues and simplifies the interconnect architecture while maintaining compact cell area.
3Ease of manufacture
If CA is used instead of M1 with narrow width, then library construct is enabled for production, but manufacturability and reliability are compromised
Solution Approach 1:
The patent employs vertical pass-through contacts instead of narrow lateral CA structures, enabling the library construct to be produced with standard manufacturing processes. The vertical dimension provides sufficient contact area and robust electrical connections, thereby maintaining both manufacturability and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces MOL congestion, maintains design rule compliance, enhances manufacturability and reliability, and allows for the same construct to be used in consecutive pitches without missing critical poly pitches, thereby saving cell area and improving yield.
Implementation Method 1
forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and between the pFET gate and the nFET gate
Data Source
AI summary
A method of forming a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains and the resulting device are provided. Embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on a p-side of the semiconductor layer and a nFET gate on a n-side of the semiconductor layer; forming a gate contact between the pFET gate and the nFET gate; forming raised source/drains on opposite sides of each of the pFET and nFET gates; and forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and below the gate contact between the pFET and nFET gates.