Silicidized 3D NAND Stacks with Insulating Support
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Solution Overview
Problem
The miniaturization of word lines and increased number of stacks in three-dimensional memory cell arrays can lead to structural collapse, compromising storage capacity and reliability in nonvolatile semiconductor memory devices.
Innovation Solution
A nonvolatile semiconductor memory device design featuring a three-dimensionally structured memory cell array with wide stacks and silicidized conductive layers, where the stacks are supported by insulating layers and connection portions to maintain structural integrity and reduce electric resistance, while increasing storage capacity by maintaining a wider stack width and increasing the number of conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the word lines are miniaturized and the number of stacks is increased to enhance storage capacity, then the storage capacity increases, but the stacked structure may collapse due to reduced structural stability
Solution Approach 1:
The patent divides the continuous word line into multiple separate conductive layers (first conductive layer, second conductive layer, third conductive layer) stacked at different heights. This segmentation allows each conductive layer to be independently supported by insulating layers, preventing structural collapse while maintaining miniaturization and increasing storage capacity through vertical stacking.
Solution Approach 2:
The patent introduces insulating layers (first insulating layer, second insulating layer, third insulating layer) as intermediary structures between conductive layers and between conductive layers and semiconductor pillars. These insulating layers act as support structures that maintain the spatial separation and structural integrity of miniaturized word lines, preventing collapse while enabling increased stacking density.
2Quantity of substance
If the number of conductive layers is increased to enhance storage capacity, then the storage capacity increases, but the electric resistance increases
Solution Approach 1:
The patent implements a nested structure where multiple conductive layers are vertically stacked within a compact space, with each conductive layer containing memory cells at different heights. This nesting approach increases storage capacity within the same footprint while maintaining short transmission paths for each layer, thereby controlling electric resistance despite the increased number of layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively inhibits stack collapse, enhances storage capacity, and reduces electric resistance, thereby improving the reliability and performance of nonvolatile semiconductor memory devices while maintaining a wide stack width and increasing the number of conductive layers.
Implementation Method 1
Each of the first conductive layers in contact with the first insulating layer includes a silicide layer
Data Source
AI summary
According to an aspect of the invention, a first insulating layer is buried in a first trench provided in at least one of an interstice between first and second semiconductor pillars, a side surface portion of the first semiconductor pillar opposed to the second semiconductor pillar, and a side surface portion of the second semiconductor pillar opposed to the first semiconductor pillar. A first trench penetrates each stack from an uppermost portion of the stack to a first conductive layer in a lowermost portion of the stack. The first trench is arranged away from a first connection portion. Each of the first conductive layers in contact with the first insulating layer includes a silicide layer.