Silicon Bridge Wafer Interconnects for CTE Stress Relief
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Solution Overview
Problem
Existing semiconductor wafer interconnect technologies face challenges in achieving high-density connections and efficient thermal management, particularly in side-by-side packaging configurations, which affect signal integrity and thermal stability.
Innovation Solution
Implementing a silicon bridge or multi-layer flex bridge for interconnecting semiconductor wafers, with signal line pitches below 1 micron, and utilizing CTE-matched substrates or thinned silicon bridges for mechanical compliance, along with through silicon vias and redistribution layers for enhanced connectivity and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional interconnection methods are used for side-by-side wafer packaging, then mechanical support and basic electrical connections are provided, but high-density signal connections with sub-micron pitch cannot be achieved
Solution Approach 1:
The patent employs multiple levels of redistribution layers (RDL1, RDL2, RDL3) stacked vertically within the interconnection structure, with each RDL providing additional wiring levels. Through-silicon vias (TSVs) penetrate the substrate to connect these nested RDL layers, enabling sub-micron pitch signal connections by utilizing the third dimension for routing complexity rather than requiring proportionally larger planar area.
2Reliability
If wafers are mounted on substrates with mismatched thermal expansion coefficients, then mechanical mounting is achieved, but thermal mechanical stress accumulates during temperature cycling
Solution Approach 1:
The patent introduces a stress compensation layer with specifically engineered thermal expansion properties positioned between the wafer and substrate. This layer's thermal expansion coefficient is designed to match that of the wafer, creating a gradient transition that compensates for the substrate's mismatched expansion characteristics during temperature cycling, thereby reducing cumulative thermal mechanical stress.
3Reliability
If rigid interconnection structures are used between wafers, then stable electrical connections are provided, but mechanical compliance and stress absorption are reduced
Solution Approach 1:
The interconnection structure combines rigid components (substrate, RDL layers, TSVs) with a compliant stress compensation layer. This composite construction provides both the structural stability needed for reliable electrical connections and the mechanical compliance necessary to absorb thermal expansion differences and accommodate manufacturing tolerances through elastic deformation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves high-bandwidth, high-density interconnects with reduced thermal mechanical stress, enabling efficient signal transmission and heat dissipation in wafer-scale systems.
Implementation Method 1
A coefficient of thermal expansion (CTE) of the two or more wafers can be matched to a CTE of the substrate
Implementation Method 2
A multilayer flex structure connects to each of the two or more wafers, where the multilayer flex structure terminates in a connector
Data Source
AI summary
An integrated circuit package provides a high bandwidth interconnect between wafers using a very high density interconnect using a silicon bridge or a multi-layer flex between wafers. In some embodiments, more than one wafer may be mounted and connected with a rigid silicon bridge onto a common substrate. This common substrate can be matched, with respect to their coefficients of thermal expansion (CTE), to the silicon wafer. The CTE matched substrate can reduce the thermal mechanical stress on the wafers and the rigid silicon bridge interconnect. In some embodiments, a thinned silicon bridge is utilized to interconnect wafers which are mounted on separate glass substrates. The thinned bridge would allow for mechanical compliance between the wafers. In some embodiments, the wafers can be mounted onto separate glass substrates and attached with a fine pitch multi-layer flex structure which provides compliance between the wafers.