Single-Crystal Silicon Channel for BiCS Memory Erase
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Solution Overview
Problem
In BiCS memory, the decrease in channel thickness and increase in the number of stacked layers lead to difficulties in ion implantation, reducing GIDL current and deteriorating erase characteristics, and decreasing channel electric current, which affects the operating speed and memory capacity.
Innovation Solution
The formation of doped silicide layers as diffusion layers and single-crystal silicon layers as the channel in the semiconductor pillar, enhancing the erase characteristic and channel current by improving the junction interface and electric field during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is performed into polysilicon channel to form diffusion layers, then erase operation can be achieved through GIDL current, but as channel thickness decreases ion implantation becomes difficult and GIDL current decreases
Solution Approach 1:
The patent changes the material parameter of the channel from polysilicon to single-crystal silicon, which fundamentally alters the implantation characteristics and enables effective diffusion layer formation even in thin channels. This material parameter change resolves the contradiction by maintaining erase capability while allowing reduced channel thickness.
Solution Approach 2:
The patent replaces ion implantation into polysilicon with a different formation mechanism for diffusion layers in single-crystal silicon channels. This substitution of the physical process enables effective diffusion layer creation through alternative mechanisms that are not limited by the thickness constraints affecting polysilicon implantation.
2Quantity of substance
If channel thickness is decreased to increase memory capacity, then more layers can be stacked, but channel electric current reduces and operating speed decreases
Solution Approach 1:
The patent changes the crystal structure parameter of the channel material from polycrystalline to single-crystal, which fundamentally improves charge carrier mobility. This parameter change enables thin channels to maintain high current flow capabilities, resolving the contradiction between increased memory capacity (through more stacked layers) and operating speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the erase characteristic and increases the channel current, addressing the limitations of thin channels and multiple layers in BiCS memory, leading to enhanced performance and capacity.
Implementation Method 1
An erase operation is performed by injecting, into a memory cell, holes generated by a GIDL (Gate-Induced Drain Leakage) current in the junction interface between the diffusion layers and channel of the selection transistor
Implementation Method 2
the mobility of electric charge decreases as the thickness of the channel decreases or the number of stacked layers increases. That is, the channel electric current reduces
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, a first layer, a first conductive layer, a second conductive layer, an insulating layer, a block insulating layer formed on an inner surface of a pair of through holes formed in the insulating layer, the second conductive layer, and the first conductive layer, and on an inner surface of a connecting hole formed in the first layer and configured, a charge storage layer formed on the block insulating layer, a tunnel insulating layer formed on the charge storage layer, and a semiconductor pillar formed on the tunnel insulating layer. The semiconductor pillar includes a doped silicide layer which is formed in the insulating layer, a silicon layer formed in the second conductive layer and the first conductive layer, and a silicide layer formed in first layer.