Silicon Channel Tempering With Ge Interface for p-Type Threshold Control
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Solution Overview
Problem
Conventional methods for forming p-type multi-bridge channel (MBC) transistors face challenges in achieving satisfactory threshold voltages due to the difficulty in identifying suitable p-type work function metals and integrating silicon germanium channels, resulting in a small process window, less-than-ideal performance, and high fabrication costs.
Innovation Solution
A method involving the deposition of a germanium cladding layer on silicon channels, followed by annealing to convert it into a silicon germanium layer, and then subjecting it to a pre-clean process to form a germanium-containing interfacial layer, which provides dipoles or fixed charges, thereby lowering the threshold voltage for p-type MBC transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods use multiple p-type work function metal layers stacked over silicon channels to achieve desired threshold voltages, then threshold voltage control is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent extracts the germanium cladding layer from the conventional multi-layer metal stack approach. Instead of stacking multiple work function metal layers, the invention uses a single germanium-containing interfacial layer formed by annealing a germanium cladding layer, thereby simplifying the structure while maintaining threshold voltage control capability
Solution Approach 2:
The patent changes the material parameter from conventional work function metals to germanium-containing materials. By controlling the germanium concentration and annealing conditions, the threshold voltage is adjusted through material composition changes rather than through multiple metal layer stacking
2Reliability
If silicon channels are replaced with silicon germanium channels to achieve desired threshold voltages, then electrical performance is improved, but integration difficulty and fabrication cost increase
Solution Approach 1:
The patent applies local quality by introducing germanium only at the channel interface region rather than throughout the entire channel. The germanium cladding layer is deposited only on specific surfaces of the silicon channel, and annealing creates a localized germanium-containing interfacial layer, maintaining silicon channel integrity while improving electrical performance at the critical interface
Solution Approach 2:
The patent performs preliminary action by depositing the germanium cladding layer before channel release and gate formation. This early introduction of germanium allows subsequent processing steps to proceed with standard silicon channel handling, avoiding the integration difficulties of post-fabrication silicon germanium channel replacement
3Manufacturing precision
If the process window is small in conventional p-type MBC transistor fabrication, then manufacturing precision is limited, but improving it requires increased process complexity
Solution Approach 1:
The patent introduces dynamics by making the germanium concentration gradient可调 (adjustable) through controlled annealing conditions. The germanium diffusion depth and concentration profile can be dynamically adjusted by varying annealing temperature and time, thereby expanding the process window without adding process steps
Solution Approach 2:
The patent uses parameter changes in the annealing process (temperature, time, atmosphere) to control germanium diffusion characteristics. By adjusting these parameters, the germanium concentration profile in the interfacial layer is optimized, expanding the process window for achieving desired threshold voltages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively lowers the threshold voltage of p-type MBC transistors, improving their performance and reducing fabrication costs by utilizing a germanium-containing interfacial layer that creates desirable electrical properties.
Implementation Method 1
performing a first anneal process to convert the germanium-containing cladding layer into a silicon germanium layer
Implementation Method 2
performing a first anneal process to convert the germanium-containing cladding layer into a silicon germanium layer
Implementation Method 3
the converted cladding layer is then subjected to a pre-clean process to form a germanium-containing oxide interfacial layer
Data Source
AI summary
A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.