Polycrystalline Silicon-Germanium Thin Film Transistor for Stacked Memory
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Solution Overview
Problem
In monolithic three-dimensional memory arrays, high-temperature processing steps cause dopant diffusion between heavily doped source and drain regions of field effect transistors, potentially shorting the channel, especially in stacked device levels, leading to undesirable performance variations.
Innovation Solution
The use of a polycrystalline silicon-germanium channel region with a two-step anneal process to minimize dopant diffusion, where a low-temperature long anneal forms larger grains and a short high-temperature anneal activates dopants, combined with a hybrid gate dielectric and ion implantation in an amorphous channel to reduce grain boundary density and dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-temperature processing steps are used to form stacked device levels, then device density and integration are improved, but dopant diffusion increases causing channel shorting and performance degradation
Solution Approach 1:
The patent changes the material parameter from pure polysilicon to silicon-germanium alloy, which has a lower melting point and enables low-temperature crystallization. This parameter change allows stacked device levels to be formed without high-temperature processing, thereby preventing dopant diffusion while maintaining device density
Solution Approach 2:
The patent uses composite silicon-germanium material instead of pure silicon. The silicon-germanium alloy forms a eutectic structure that crystallizes at lower temperatures, enabling the formation of multiple stacked device levels without the high-temperature processing that causes dopant diffusion in conventional polysilicon devices
2Speed
If the channel length is reduced to increase device speed, then operation speed is improved, but dopant diffusion from source and drain regions increases causing channel shorting
Solution Approach 1:
The patent changes the crystallization temperature parameter by using silicon-germanium material, enabling the channel to be formed at low temperatures before dopant implantation. This allows shorter channel lengths to be fabricated without the risk of dopant diffusion that plagues conventional short-channel devices
Solution Approach 2:
The patent performs low-temperature crystallization of the silicon-germanium channel layer before dopant implantation. This preliminary action establishes the channel structure at low temperature, preventing subsequent dopant diffusion even when channel length is reduced for faster operation
3Quantity of substance
If multiple stacked device levels are formed, then memory capacity is improved, but repeated high-temperature steps cause cumulative dopant diffusion
Solution Approach 1:
The patent fundamentally changes the processing temperature parameter by using silicon-germanium's low-temperature crystallization property. This enables the formation of multiple stacked device levels without repeated high-temperature steps, thereby preventing cumulative dopant diffusion while increasing memory capacity
Solution Approach 2:
The patent performs all channel crystallization operations at low temperatures before any high-temperature dopant activation steps. This preliminary low-temperature crystallization prevents dopant diffusion during the formation of multiple stacked levels, maintaining precise dopant distribution control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes dopant diffusion and enhances carrier mobility, reducing off-current and maintaining device performance consistency across multiple stacked device levels, while allowing for faster device operation and reduced leakage current.
Implementation Method 1
a low-temperature long anneal forms larger grains and a short high-temperature anneal activates dopants
Implementation Method 2
minimize dopant diffusion
Implementation Method 3
ion implantation in an amorphous channel
Data Source
AI summary
Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.