High-Resistivity Silicon Handle Wafer Flatness for Hybrid Bonding
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Solution Overview
Problem
High-resistivity silicon handle wafers for hybrid substrate structures face challenges in achieving precise geometric control and flatness, particularly due to non-circular asymmetry caused by crystal orientation identifiers, which limits the performance of devices like piezoacoustic thin film surface acoustic wave filters.
Innovation Solution
A manufacturing method involving controlled single-side fixed abrasive grinding and polishing processes, combined with optical and capacitive measurements, to achieve submicron total thickness variation and enhance the flatness of 150-200 mm-diameter silicon handle wafers, addressing the geometric influence of crystal orientation identifiers and enabling higher precision in hybrid substrate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a crystal orientation identifier is produced on the wafer, then the wafer can be properly oriented for processing, but non-circular asymmetry is introduced that degrades flatness and thickness uniformity
Solution Approach 1:
The patent applies preliminary anti-action by intentionally introducing a counter-asymmetric element during grinding that compensates for the asymmetric distortion caused by the crystal orientation identifier. The chuck arrangement is designed to apply non-uniform pressure or positioning that pre-corrects for the expected deformation, allowing the identifier to remain while its harmful geometric influence is neutralized.
Solution Approach 2:
The patent utilizes asymmetry by designing the chuck arrangement to deliberately apply asymmetric forces or constraints during the grinding process. This asymmetric processing compensates for the asymmetric distortion introduced by the crystal orientation identifier, transforming the problem of asymmetry into a solution through controlled asymmetric correction.
2Length of moving object
If the wafer thickness is reduced to achieve thin active layers, then device performance is improved, but the geometric accuracy and flatness become more critical and difficult to control
Solution Approach 1:
The patent applies preliminary action by performing asymmetric compensation during the grinding process before the final thinning and bonding steps. The chuck arrangement corrects geometric deviations in the handle wafer while it still has sufficient thickness to accommodate the correction, ensuring that subsequent thinning operations maintain the corrected geometry without introducing additional asymmetries.
3Ease of manufacture
If standard grinding processes are used, then the manufacturing process is simple, but the total thickness variation exceeds the submicron requirement
Solution Approach 1:
The patent applies dynamics by implementing a controllable, adjustable chuck arrangement that can dynamically adapt its pressure distribution or positioning during the grinding process. This dynamic control allows the system to compensate for the asymmetric influence of the crystal orientation identifier in real-time, achieving submicron thickness variation without requiring completely complex manufacturing procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly improves the flatness and geometric accuracy of high-resistivity silicon handle wafers, achieving desired submicron total thickness variation and enabling superior performance in hybrid substrate structures, such as piezoacoustic thin film surface acoustic wave filters, by effectively compensating for non-circular asymmetry and enhancing the bonding of active layers.
Implementation Method 1
The step of thinning comprises a controlled single-side, fixed abrasive grinding of the produced, crystal orientation identifier-comprised wafer
Implementation Method 2
a step of polishing the passivation layer from the certain layer thickness to a desired final layer thickness of the passivation layer
Data Source
AI summary
The application relates to a manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure. The method comprises a step of producing the wafer having a crystal orientation identifier and a certain thickness. The method further comprises a step of thinning the produced wafer from the certain thickness to a desired thickness of the wafer in order to obtain the thinned wafer. The method further comprises a step of providing a surface passivation layer having a certain layer thickness on a front surface of the thinned wafer. The method further comprises a step of polishing the passivation layer from the certain layer thickness to a desired final layer thickness of the passivation layer so that the polished front surface of the wafer enables active layer bonding in order to form the hybrid substrate structure.