Silicon Interposer Fan-Out for 3D IC Package Height Reduction
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing device density and interconnect complexity in two-dimensional integrated circuits, leading to increased circuit resistance-capacitance delay and power consumption, which are addressed by transitioning to three-dimensional integrated circuits (3D ICs) but still encounter issues with coefficient of thermal expansion (CTE) mismatch and manufacturing costs.
Innovation Solution
The use of silicon interposers between silicon dies and organic substrates to fan out metal pitches, reducing CTE mismatch and eliminating the need for organic substrates, while incorporating through-silicon vias (TSVs) and molding compound materials to enhance interconnect structures and reduce package height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2D integrated circuits are used to increase device density, then more components can be integrated into a given area, but circuit resistance-capacitance delay and power consumption increase significantly
Solution Approach 1:
The patent transitions from conventional 2D integrated circuit layout to 3D stacked architecture, where multiple semiconductor layers are vertically stacked and interconnected through through-silicon vias. This dimensional change allows devices to be arranged in three-dimensional space rather than confined to a single plane, dramatically increasing device density while reducing interconnect lengths and associated power consumption.
2Quantity of substance
If more devices are put into one chip to increase integration density, then more components are integrated, but the number and length of interconnections increase leading to increased RC delay
Solution Approach 1:
By stacking semiconductor layers vertically and connecting them through short through-silicon vias, the patent reduces the horizontal distance signals must travel compared to 2D layouts. The vertical interconnects provide direct pathways between layers, significantly reducing interconnection length and RC delay while enabling higher integration density.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor layers are stacked one on top of another, with each layer containing devices and interconnections. The layers are interconnected through through-silicon vias that pass through the substrate, creating a compact nested architecture that reduces overall interconnect length compared to planar expansions.
3Reliability
If silicon interposers are used to fan out metal pitches and reduce CTE mismatch, then reliability improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent uses silicon interposers with the same material composition as the semiconductor devices they support, creating a homogeneous structure with matched coefficient of thermal expansion (CTE). This material homogeneity eliminates CTE mismatch issues that arise when dissimilar materials are bonded together, improving reliability during thermal cycling while maintaining compatible processing conditions.
Solution Approach 2:
The silicon interposer serves as an intermediary substrate between the semiconductor die and the organic package substrate. It provides a transition layer that fans out the fine-pitch metal interconnections from the die to the coarser pitch required by the package substrate, while its silicon material properties ensure CTE matching with the semiconductor devices, reducing stress and improving reliability.
4Length of stationary object
If through-silicon vias are used to interconnect stacked wafers, then wire length is reduced and device density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms through-silicon vias and establishes interconnect structures in the semiconductor layers before the stacking and bonding processes. This preliminary formation of vias and interconnects allows for precise alignment and integration, as the structures are already in place to receive and align with corresponding features from adjacent layers during the stacking process.
Data Source
AI summary
A package system includes a first interposer including a first substrate having first and second primary surfaces on opposite sides of the first substrate. The package system includes a first interconnect structure over the first surface, the first interconnect structure having a first metallic line pitch LP1. The package system includes a plurality of first through silicon via (TSV) structures in the first substrate. The package system includes a molding compound material partially enveloping the first substrate. The package system includes a plurality of through vias in the molding compound material, wherein each through via of the plurality of through vias is offset from the first substrate. The package system includes a second interconnect structure on a second surface of the first substrate. The second interconnect structure has a second metallic line pitch LP2, and LP2>LP1. The package system includes a first integrated circuit over the first interposer.