Silicon Interposer Polyimide Cap Layer CTE Matching
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Solution Overview
Problem
Conventional 3D IC package systems face challenges in reducing manufacturing costs and preventing thermal expansion mismatch issues between materials, leading to delamination and bump failures during assembly and reliability tests.
Innovation Solution
The use of a silicon interposer with a polyimide cap layer and a molding compound layer, where the coefficient of thermal expansion (CTE) of the underfill material and cap layer is matched to the molding compound layer to prevent delamination and bump failures, and the formation of through-silicon-via (TSV) structures is optimized to reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D IC package systems are used with standard materials, then manufacturing process is simpler, but thermal expansion mismatch causes delamination and bump failures
Solution Approach 1:
A polyimide cap layer is introduced as an intermediary between the silicon interposer and the molding compound layer. This cap layer acts as a thermal expansion buffer that accommodates the CTE mismatch between the silicon interposer (low CTE) and the molding compound (high CTE), preventing delamination and bump failures during thermal cycling while maintaining manufacturing feasibility
Solution Approach 2:
The package system employs a composite material structure consisting of multiple layers with different CTE characteristics (silicon interposer, polyimide cap layer, molding compound layer, underfill material). Each material is selected for its specific CTE properties to create a gradient that gradually transitions from low to high expansion, distributing thermal stress across the structure rather than concentrating it at single interfaces
2Ease of manufacture
If silicon interposer with polyimide cap layer and optimized TSV structures are used, then manufacturing cost is reduced, but thermal expansion matching becomes more critical
Solution Approach 1:
The polyimide cap layer's CTE parameter is specifically selected to fall between the CTE values of silicon and molding compound. By changing the material parameter (CTE) of the cap layer, the system achieves a gradual CTE transition that reduces thermal stress without requiring expensive alternative materials or complex design modifications
Solution Approach 2:
The polyimide cap layer is applied locally only at the critical interface between the silicon interposer and molding compound, where thermal expansion mismatch is most severe. This localized application of a specific material property addresses the thermal stress problem at the most vulnerable point without increasing complexity throughout the entire package structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cost of manufacturing 3D IC package systems while ensuring reliability by minimizing thermal expansion mismatches and maintaining electrical connections, thereby enhancing the assembly and reliability of the package systems.
Implementation Method 1
the coefficient of thermal expansion (CTE) of the underfill material and cap layer is matched to the molding compound layer to prevent delamination and bump failures
Data Source
AI summary
A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.