Silicon-Layer Silicide Contacts for Low-Loss FinFET Source/Drain
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the efficient integration of silicide regions in semiconductor devices, particularly in FinFETs, to minimize the consumption of silicon germanium and reduce resistance while maintaining consistent thickness and controlling dopant buildup.
Innovation Solution
The formation of a silicide region using a silicon and metal layer, such as titanium, deposited over silicon germanium, which interacts during annealing to form a metal silicide, minimizing silicon germanium consumption and enhancing the contact area between the source/drain and silicide layer, thereby reducing resistance and maintaining thickness consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer (e.g., titanium) is deposited over silicon germanium to form a silicide region, then electrical connectivity is improved and resistance is reduced, but silicon germanium is consumed and extrusion occurs
Solution Approach 1:
A silicon layer is deposited over the silicon germanium source/drain region before metal deposition. This preliminary silicon layer acts as a reservoir that reacts with the metal during annealing to form silicide, preventing the metal from consuming the silicon germanium and causing extrusion while still achieving low-resistance electrical connectivity.
Solution Approach 2:
The silicon layer serves as an intermediary between the metal and silicon germanium. It mediates the silicide formation process by providing silicon atoms to react with the metal, thereby protecting the silicon germanium from direct interaction and consumption, while enabling the formation of a conductive silicide contact.
2Reliability
If metal and silicon layers are annealed to form silicide, then contact area between source/drain and silicide is enhanced, but dopant buildup occurs
Solution Approach 1:
The dopant management function is extracted from the silicide formation process. By using a separate silicon layer that is depleted of dopants (or has controlled dopant content), the dopant buildup problem is isolated and removed from the critical source/drain region, allowing silicide formation to proceed without contaminating the active device areas with excess dopant.
3Productivity
If continuous reductions in minimum feature size are implemented, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The contact formation process is segmented into distinct functional layers: a silicon layer deposited over the source/drain region, followed by a metal layer. This segmentation allows independent optimization of each layer's properties and simplifies process control, enabling scaling to smaller feature sizes without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces extrusion of titanium and minimizes dopant buildup, improving electrical connectivity and reducing resistance in the silicide region, thus enhancing the performance of semiconductor devices like FinFETs.
Implementation Method 1
annealing at least the silicon layer and the titanium layer to form a titanium-silicide layer
Data Source
AI summary
A semiconductor device includes a semiconductor channel. The semiconductor device includes a metal gate structure disposed over the semiconductor channel. The semiconductor device includes a gate electrode having a bottom surface contacting an upper surface of the metal gate structure. The gate electrode has its side portions extending from its top surface toward the semiconductor fin with a first depth and a central portion extending from its top surface toward the semiconductor fin with a second depth, the first depth being substantially greater than the second depth.