Silicon Nanotube Memory Cell for Leakage Reduction
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Solution Overview
Problem
Conventional non-volatile memory cells face challenges such as short channel effects, coupling ratio, lithography limitations, and crosstalk due to charge storage layers and control gates, leading to high leakage currents and poor retention characteristics, especially when scaling below the 32-nm technology node.
Innovation Solution
A silicon nanotube field effect transistor-based memory cell structure is developed, featuring a nanotube trench with a tunnel oxide layer, charge trapping layer, and blocking oxide layer, which mechanically separates the nanotube structure from the substrate, allowing for ultra-short channel devices and reduced parasitic capacitance, and is formed using a CMOS-compatible process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional non-volatile memory devices are scaled below the 32-nm technology node, then higher density is achieved, but leakage currents increase due to short channel effects, drain induced barrier lowering, and sub-surface punch-through effect
Solution Approach 1:
The patent transitions from planar memory cell architecture to a three-dimensional vertically-coupled architecture. The charge trapping layer is positioned vertically above the channel region, and the control gate is stacked above the charge trapping layer, creating a vertical tunneling path that enables higher density while maintaining control over leakage currents through the oxide layers.
Solution Approach 2:
The memory device is segmented into distinct functional layers: a substrate with semiconductor layer, a charge trapping layer, and a control gate layer. This segmentation allows independent optimization of each layer's properties to address leakage currents while maintaining high density.
2Quantity of substance
If the tunnel oxide thickness is reduced to achieve higher density, then more charges can be stored, but reliability deteriorates due to back-tunneling and leakage of stored charges
Solution Approach 1:
The patent employs a composite oxide structure consisting of a first oxide layer (tunnel oxide) and a second oxide layer (blocking oxide) with different dielectric properties. The first oxide layer enables charge injection, while the second oxide layer prevents charge loss, creating a reliable charge storage mechanism even with thin oxide layers.
Solution Approach 2:
The charge trapping layer acts as an intermediary between the substrate and control gate, providing a dedicated storage region that decouples the tunneling process from the charge retention mechanism, allowing thin oxide layers without compromising reliability.
3Quantity of substance
If memory cells are closely packed to increase density, then higher capacity is achieved, but crosstalk increases due to coupling capacitance between adjacent cells
Solution Approach 1:
By moving the charge storage function to a vertical layer above the channel, the patent reduces horizontal overlap between adjacent memory cells. This vertical separation minimizes coupling capacitance between neighboring cells while maintaining high density through vertical stacking.
4Ease of manufacture
If conventional planar memory architecture is used, then manufacturing is simpler, but short channel effects and coupling ratio issues limit further scaling
Solution Approach 1:
The patent maintains manufacturing compatibility by using standard semiconductor fabrication processes to create the vertical structure. The vertically-coupled architecture is built using sequential deposition and patterning steps that are extensions of conventional planar processing, enabling short channel control without requiring entirely new manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution addresses short channel effects and coupling issues, enabling efficient energy management and improved retention characteristics by reducing leakage currents and parasitic capacitance, thus enhancing the performance and density of memory devices.
Implementation Method 1
tunnel oxide layer
Implementation Method 2
charge trapping layer
Data Source
AI summary
A memory cell includes a substrate and a body including plural layers. The body has an inner body and an outer body, and the body is formed on top of the substrate. A nanotube trench is formed vertically in the body and extends to the substrate. A nanotube structure is formed in the nanotube trench. The nanotube trench divides the body into the inner body and the outer body and the nanotube structure is mechanically separated from the inner body and the outer body by a tunnel oxide layer, a charge trapping layer, and a blocking oxide layer.