Silicon Patch Interconnects for High Density I/O in Microelectronic Packages
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Solution Overview
Problem
The increasing integration of multiple dies in CPU packages and miniaturization trends lead to a limitation in die connections per millimeter, resulting in insufficient bandwidth and inadequate I/O density, which current scaling methods like C4 interconnects and substrate Line/Spaces cannot adequately address.
Innovation Solution
Embedding silicon patches with high-density solder bumps and fine lines in the substrate, connected by electrically conductive lines, to increase I/O density and reduce thermal expansion mismatch, enabling higher bandwidth and mechanical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional C4 interconnect scaling is used to increase I/O density, then manufacturing process simplicity is maintained, but the maximum achievable I/O density is limited and insufficient for future multi-chip module requirements
Solution Approach 1:
The patent employs a composite interconnect structure combining wire bonds (traditionally used for coarser pitch connections) with solder bumps (for fine pitch connections). This composite approach allows the system to achieve higher I/O density by integrating two different interconnect technologies, where wire bonds provide robust connections for certain signals while solder bumps enable finer pitch connections for other signals, thereby overcoming the limitations of single-technology scaling
Solution Approach 2:
The interconnect structure is segmented into multiple types: wire bonds for certain connections and solder bumps for others. This segmentation allows each interconnect type to be optimized for its specific function, with wire bonds handling connections where their mechanical strength and established process advantages are beneficial, and solder bumps handling connections requiring finer pitch. This segmented approach enables higher overall I/O density without requiring complete redesign of all interconnect pathways
2Quantity of substance
If substrate Line/Space scaling is used to increase I/O density, then existing substrate manufacturing processes are maintained, but thermal expansion mismatch increases causing mechanical reliability issues
Solution Approach 1:
The patent changes the material parameter (thermal expansion coefficient) by introducing a low-CTE substrate material. This parameter change directly addresses the thermal expansion mismatch problem because the low-CTE material better matches the thermal expansion characteristics of the attached chips, thereby reducing mechanical stress and improving reliability while still enabling high I/O density through the composite wire bond/solder bump interconnect approach
3Productivity
If higher I/O density is achieved through miniaturization, then bandwidth capability is limited by insufficient die connections, but further miniaturization increases manufacturing difficulty and reduces mechanical reliability
Solution Approach 1:
The patent employs a dynamic hybrid interconnect approach where different interconnect types (wire bonds and solder bumps) are used in different locations and for different signals based on specific requirements. This dynamic allocation allows the system to achieve high I/O density and bandwidth capability without requiring all connections to be miniaturized to the same extent, thereby maintaining manufacturing feasibility and mechanical reliability while still achieving the necessary productivity improvement
Data Source
AI summary
A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.