Silicon-Rich Middle Layer for FinFET Lithography Uniformity
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Solution Overview
Problem
In semiconductor manufacturing, the use of FinFETs with three-dimensional fin structures leads to unevenness in interlayer dielectric layers, causing performance issues during lithography operations, and existing tri-layer or bi-layer resist systems experience critical dimension variations that become more significant as pattern sizes shrink.
Innovation Solution
A multi-layer resist patterning system is developed, where a middle layer with 50 wt% or more silicon is used to suppress critical dimension variations during etching operations, employing a silicon-containing solution with silicon particles or clusters and organic ligands, and an annealing process to ensure smooth patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFETs with three-dimensional fin structures are used to increase device density, then device density and performance are improved, but unevenness in interlayer dielectric layers is caused, leading to lithography performance issues
Solution Approach 1:
The patent divides the lithography process into multiple patterning steps using separate resist layers (first resist layer 136, second resist layer 138) to address the unevenness caused by three-dimensional fin structures. Each layer handles specific patterning requirements, allowing the system to overcome surface irregularities that would affect single-layer lithography performance.
Solution Approach 2:
The patent introduces an additional layer dimension by forming a second resist layer over the first resist layer. This multi-layer approach adds vertical dimensionality to the patterning process, enabling compensation for surface unevenness and achieving uniform pattern transfer despite variations in the interlayer dielectric layer topography.
2Manufacturing precision
If tri-layer or bi-layer resist systems are used for patterning, then pattern formation capability is improved, but critical dimension variations become more significant as pattern sizes shrink
Solution Approach 1:
The patent modifies material parameters by selecting resist materials with specific properties for each layer. The first resist layer uses a material with etch selectivity relative to the second resist layer, while the second resist layer uses a material optimized for maintaining critical dimensions during etching. This parameter optimization across multiple layers reduces critical dimension variations.
Solution Approach 2:
The patent employs composite material strategy by combining different resist materials in a multi-layer system. Each resist layer is composed of materials with tailored properties (etch selectivity, adhesion, pattern fidelity) that work together to achieve superior critical dimension control compared to single-material systems.
3Manufacturing precision
If multi-layer resist patterning system is implemented to reduce critical dimension variations, then pattern size control is improved, but process complexity increases
Solution Approach 1:
The patent applies local quality by assigning specific functions to specific layers: the first resist layer is optimized for initial pattern definition with appropriate etch selectivity, while the second resist layer is optimized for critical dimension preservation. Each layer has locally optimized properties that address specific aspects of the patterning challenge, making the complex process manageable through functional decomposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces critical dimension variations between patterned layers, improving pattern size control and etching selectivity, thereby enhancing the precision and reliability of semiconductor device manufacturing.
Implementation Method 1
an annealing process to ensure smooth patterning
Data Source
AI summary
In a pattern formation method, a bottom layer is formed over an underlying layer. A middle layer is formed over the bottom layer. A resist pattern is formed over the middle layer. The middle layer is patterned by using the resist pattern as an etching mask. The bottom layer is patterned by using the patterned middle layer. The underlying layer is patterned. The middle layer contains silicon in an amount of 50 wt % or more and an organic material. In one or more of the foregoing and following embodiments, an annealing operation is further performed after the middle layer is formed.