Thin Semiconductor Package Frame With Laser-Patterned Silicon Vias

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Solution Overview

Problem

Conventional semiconductor device packages face limitations in scalability, material structuring resolution, and high costs due to the use of organic package substrates and silicon interposers, particularly in forming fine features and addressing coefficient of thermal expansion mismatch, leading to decreased power efficiency and increased manufacturing costs.

Innovation Solution

The development of thin-form-factor semiconductor device packages using a core frame made of silicon with integrated vias and insulating layers, structured through micro-blasting or direct laser patterning, allowing for fine feature formation and reduced thermal expansion issues, thereby enhancing die-to-package area ratios and through-package bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If organic package substrates are used, then ease of manufacture and low cost are achieved, but material structuring resolution becomes insufficient for high circuit density

Engineering Contradiction:
Improveease of manufactureVSAvoidmaterial structuring resolution
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent transitions from organic substrates to silicon-based core frames, fundamentally changing the material parameter to achieve both high manufacturing precision for fine features and cost-effectiveness through standardized silicon processing techniques

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention uses composite structures combining silicon core frame with insulating materials (such as oxide or nitride layers) to create a package substrate that achieves both high resolution structuring capability and manufacturing efficiency

Inventive Principle:
Principle #40Composite materials

2Power

If silicon interposers are used, then high bandwidth density and lower power consumption are achieved, but manufacturing cost increases due to complex processing

Engineering Contradiction:
Improvepower efficiencyVSAvoidmanufacturing cost
Core Design Contradiction:
PowerVSEase of manufacture

Solution Approach 1:

The patent extracts the essential function of silicon interposers (high bandwidth density and power efficiency) while removing the costly complex processing steps by using simplified core frame structures with integrated cavities and via holes formed through micro-blasting or laser patterning

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention segments the silicon core frame into functional regions with integrated cavities for semiconductor chips and via holes for electrical connections, achieving interposer-like performance through modular design that simplifies manufacturing

Inventive Principle:
Principle #1Segmentation

3Area of moving object

If feature size is reduced for scaling, then device footprint is reduced, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvedevice footprintVSAvoidmanufacturing complexity
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The patent replaces conventional mechanical lithography and etching methods with micro-blasting or direct laser patterning techniques that can directly form fine features and cavities in silicon, achieving small device footprint while simplifying the manufacturing process by reducing the number of processing steps

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables efficient and cost-effective formation of semiconductor device packages with improved scalability, reduced mechanical defects, and enhanced power efficiency by utilizing silicon-based core frames with integrated vias and insulating layers, addressing the limitations of conventional materials.

Implementation Method 1

the core frame formed of a core frame material that comprises silicon

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

an insulating layer disposed between the via surface and the electrical interconnection

Methodology Applied
Scientific EffectElectrical resistance: Electrical Resistance

Data Source

PatentUS20260040980A1Semiconductor device packages
Publication Date: 2026.02.05 APPLIED MATERIALS INC
  • US20260040980A1 patent drawing
  • US20260040980A1 patent drawing
  • US20260040980A1 patent drawing

AI summary

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded double-sided dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.