Silver Layer Eutectic Bonding for Chip Carrier Reliability

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Solution Overview

Problem

Existing electronic circuit arrangements face challenges in achieving stable, high thermal and electrical conductivity connections between semiconductor chips and chip carriers, particularly due to issues with lead-containing soldering layers causing toxicity and whisker formation, and the limitations of palladium-containing alloys in eutectic bonding.

Innovation Solution

A silver layer is introduced as an adapter between the soldering layer and the bonding layer on the chip contact location for eutectic bonding, using a lead-free soldering layer with a predominantly palladium composition, and a three-layer structure of nickel, palladium, and gold, allowing for high conductivity and avoiding whisker formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If lead-containing soldering layers are used, then good electrical and thermal conductivity is achieved, but toxicity increases and environmental harm occurs

Engineering Contradiction:
Improveelectrical and thermal conductivityVSAvoidtoxicity
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A silver layer is introduced as an intermediary between the lead-free soldering layer and the bonding layer. This silver layer enables eutectic bonding while allowing the use of environmentally friendly lead-free soldering materials, thus resolving the contradiction between conductivity requirements and toxicity concerns

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the material composition parameters by using a predominantly palladium-containing soldering layer instead of lead-containing materials. This parameter change maintains bonding effectiveness while eliminating toxicity, achieving both good conductivity and environmental safety

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If tin-plated chip carriers are used, then ease of soldering is improved, but whisker formation occurs causing short circuits

Engineering Contradiction:
Improveease of solderingVSAvoidwhisker formation
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The silver layer acts as a protective intermediary between the tin-plated substrate and the bonding process. This intermediary prevents direct interaction that would cause whisker formation while still allowing effective eutectic bonding to occur, thus eliminating harmful effects while maintaining manufacturing ease

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention extracts the problematic tin layer from direct contact with the bonding process by placing the silver layer in between. This separation removes the source of whisker formation while preserving the beneficial soldering properties of the tin-plated substrate

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If palladium-containing soldering layers are used to avoid whiskers, then reliability is improved, but eutectic bonding capability is lost

Engineering Contradiction:
Improvestability and reliabilityVSAvoideutectic bonding capability
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The bonding interface is segmented into multiple functional layers: a palladium-containing soldering layer for reliability and whisker prevention, and a separate silver layer for eutectic bonding capability. This segmentation allows each layer to perform its specific function optimally without compromise

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention creates a composite structure at the bonding interface by combining palladium-containing material for stability with a silver layer for bonding. This composite approach integrates the advantages of both materials, achieving both reliability and eutectic bonding capability

Inventive Principle:
Principle #40Composite materials

4Reliability

If wire bonding is used to connect chip to carrier, then electrical connections are established, but the chip contact location area is underutilized

Engineering Contradiction:
Improveelectrical connectionsVSAvoidchip contact location area utilization
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention replaces the mechanical wire bonding system with a direct eutectic bonding system using the silver layer. This substitution eliminates the need for wires and enables direct bonding across the entire chip contact location area, maximizing space utilization while maintaining reliable electrical connections

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides a stable, ecologically safe connection with high thermal and electrical conductivity between the chip and chip carrier, preventing whisker formation and ensuring reliable bonding without environmental harm, while allowing for further processing and soldering onto printed circuit boards.

Implementation Method 1

A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location

Methodology Applied
Scientific EffectEutectic bonding: Melting

Data Source

PatentUS8039971B2Electronic circuit arrangement
Publication Date: 2011.10.18 INFINEON TECHNOLOGIES AG
  • US8039971B2 patent drawing
  • US8039971B2 patent drawing
  • US8039971B2 patent drawing

AI summary

Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location.