SIMD Bank Socket Interconnects With Credit-Based Data Flow
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Solution Overview
Problem
Computing devices with SIMD architecture face challenges in efficiently communicating data and information among processing elements due to logistical issues in transporting information where it is needed.
Innovation Solution
The use of sockets and busses to facilitate efficient communication of information with reduced overhead, utilizing credit-based mechanisms to manage data flow and buffer capacity between processing-element banks of integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If SIMD architecture is used for parallel processing, then processing speed is improved, but data communication efficiency among processing elements deteriorates
Solution Approach 1:
The system segments processing elements into multiple banks, each with dedicated sockets and buffers. This segmentation allows independent data communication paths for each bank, eliminating communication bottlenecks while maintaining parallel processing capability. Each bank can independently manage its data flow through dedicated sockets to memory or I/O devices.
Solution Approach 2:
Socket interfaces with integrated buffers act as intermediaries between processing element banks and memory/I/O devices. These sockets receive data from processing elements, store it in buffers, and manage transfer to destination, thereby decoupling the processing banks from direct memory access requirements and improving communication efficiency.
2Adaptability or versatility
If complex address management is implemented for data transport, then data routing capability is improved, but system complexity increases
Solution Approach 1:
The socket interface with integrated buffer automatically manages data routing and buffer management without requiring complex external address management. The socket independently handles data reception from processing elements, buffer allocation, and data transfer to memory or I/O devices, simplifying the overall system architecture while maintaining flexible data routing capability.
3Productivity
If data flow between processing elements is increased, then processing capability is improved, but data overload and communication bottlenecks worsen
Solution Approach 1:
Buffers are pre-configured at socket interfaces before data transfer begins. This preliminary action allows the system to prepare storage capacity in advance, enabling high-rate data flow from processing elements without causing overload. The pre-configured buffers absorb data bursts and regulate flow to destination, preventing communication bottlenecks.
Solution Approach 2:
The socket interface with buffer provides feedback control on data flow between processing elements and memory/I/O devices. The buffer status information feeds back to the processing elements and sockets, enabling dynamic regulation of data transfer rates to prevent overload while maintaining high processing capability.
Data Source
AI summary
An example device includes a plurality of integrated circuits. Each integrated circuit includes a set of banks. Each bank includes an array of processing elements configured for single instruction, multiple data (SIMD) operations. The device further includes a set of sockets and an external interface. Each socket is configurable to connect to any bank selected from the set of banks. The external interface is connected to the set of sockets. At least two external interfaces of respective integrated circuits are connected for bidirectional communication between the respective integrated circuits. Respective sockets of the respective integrated circuits are connectable to exchange credit for data between two respective banks.