SIMD Instruction Queues for Flexible Array Control Without Blocking
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Solution Overview
Problem
Computing devices with single instruction, multiple data (SIMD) architecture face a tradeoff between instruction flexibility and control efficiency, leading to issues such as blocking and increased execution time due to data dependency among processing elements.
Innovation Solution
Implementing multiple instruction queues and array controllers to manage instruction sequences, allowing independent operation of processing element arrays and reducing the likelihood of blocking by ensuring continuous data flow through the use of FIFO buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing elements are controlled by a single controller in SIMD architecture, then control efficiency is improved, but instruction flexibility deteriorates
Solution Approach 1:
The patent divides the control function into multiple independent array controllers, each responsible for a specific subset of processing elements. This segmentation allows each controller to independently manage its assigned PEs, providing instruction flexibility for different data types and operations while maintaining overall system efficiency through coordinated control of multiple arrays.
2Productivity
If processing elements operate in parallel with data dependencies, then productivity is improved, but blocking increases execution time
Solution Approach 1:
The patent introduces instruction queues that pre-load instructions and data into the processing element arrays before actual computation begins. This preliminary action ensures that when processing elements need data, it is already ready, eliminating blocking delays and allowing continuous parallel execution without waiting for data dependencies to resolve.
Solution Approach 2:
The patent implements continuous data flow through processing elements using FIFO buffers and instruction queues that maintain steady supply of instructions and data. This ensures processing elements operate continuously without idle waiting, maximizing parallel productivity while eliminating execution time losses from blocking and data dependency delays.
Data Source
AI summary
An example device includes single instruction, multiple data (SIMD) processing elements arranged in arrays. Array controllers are connected to the arrays of processing elements to control the arrays of processing elements to execute instructions in a SIMD fashion. An instruction queue is connected to an array controller. The instruction queue queues a sequence of instructions and dequeues the sequence of instructions to the array controller. Multiple instruction queues may be used. A main controller provides sequences of instructions to the instruction queues.