SIMD Operand Permutation via Cross-Thread Routing Circuitry
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Solution Overview
Problem
Traditional SIMD architectures face inefficiencies in sharing data among threads, leading to high power consumption and performance issues during operations like convolution and neighborhood filtering, as each thread processes data from its private storage without substantial data sharing.
Innovation Solution
The introduction of routing circuitry that selects operands from multiple architectural registers across threads in a SIMD group, facilitating data sharing and reducing the need for shared memory access through instructions like shift and fill, which permute operand data across threads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional SIMD architectures process data from private storage without sharing, then thread independence is maintained, but power consumption increases and performance decreases for operations requiring neighborhood data
Solution Approach 1:
The patent merges data from multiple thread-specific registers into a unified routing structure, allowing threads to access neighboring pixel data without separate memory accesses. The routing circuitry combines inputs from multiple registers (R0-R7) and selectively routes them to execution units, enabling efficient data sharing while maintaining thread independence.
Solution Approach 2:
The patent introduces routing circuitry as an intermediary between thread-specific registers and execution units. This mediator selectively routes data from any register to any execution unit based on control signals, enabling efficient data sharing for neighborhood operations without requiring threads to access shared memory directly.
2Productivity
If routing circuitry is introduced to select operands from multiple registers, then data sharing efficiency improves, but device complexity increases
Solution Approach 1:
The patent segments the routing function into multiple independent stages: first-stage multiplexers select from four registers for each execution unit, second-stage multiplexers select between the first-stage outputs and fill registers. This segmentation allows complex routing functionality to be built from simpler, modular components that can be independently controlled and maintained.
Solution Approach 2:
The patent implements dynamic routing where control signals (s0_sel[2:0], s1_sel[2:0]) dynamically configure the routing paths based on the specific operation being performed. The same physical circuitry can route different data combinations for different instructions, allowing the system to adapt its data flow patterns without physical reconfiguration.
3Use of energy by moving object
If shared memory access is reduced through register-based routing, then power consumption decreases, but the ability to handle diverse data sharing patterns is limited
Solution Approach 1:
The patent creates a universal routing structure that can handle multiple data sharing patterns through a single mechanism. The same routing circuitry supports horizontal shifts, vertical shifts, diagonal accesses, and arbitrary register-to-execution-unit mappings by dynamically configuring control signals, eliminating the need for separate hardware paths for each access pattern.
Solution Approach 2:
The patent changes the control parameters (selection signals) to dynamically reconfigure the data flow paths without changing the physical hardware. By varying the control signal values, the system can switch between different data sharing patterns such as neighbor access, diagonal access, or broadcast operations, maintaining versatility while using a fixed, power-efficient hardware structure.
Data Source
AI summary
Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.