Simulating Memory Cell Sensing for Testing Circuitry
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Solution Overview
Problem
Current semiconductor memory systems face challenges in testing memory operations without a memory structure, particularly in verifying the correct operation of control circuitry and sense blocks, which limits early product development and increases development time.
Innovation Solution
The proposed solution involves a control circuit that can simulate sensing of non-volatile memory cells on a semiconductor die, allowing for the testing of memory operations and verification of correct die functionality without being connected to a memory structure, enabling early testing of control semiconductor dies and optimizing memory and peripheral circuitry processing technologies separately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sense blocks are connected to a memory structure for testing, then accurate sensing operation verification is achieved, but device complexity and development time increase
Solution Approach 1:
The patent creates a copy of the sensing operation by generating simulated sense node voltages that mimic the electrical behavior of actual memory cell sensing. Instead of connecting to real memory cells, the control circuit reproduces the voltage patterns and signals that would normally be produced during sensing, allowing verification of sense block functionality without physical memory structure connection.
Solution Approach 2:
The patent introduces an intermediary simulation mechanism where the control circuit acts as a mediator between the sense blocks and the absence of memory structure. By generating intermediate test signals and simulated sense node voltages, the control circuit enables the sense blocks to operate in a test mode that verifies their functionality without requiring actual memory cells, thus decoupling the testing requirement from the physical memory structure.
2Reliability
If memory structure is integrated with control circuitry for testing, then complete system verification is achieved, but development time and manufacturing flexibility are reduced
Solution Approach 1:
The patent segments the memory system into separate functional components: the control circuit with sense blocks can be tested independently from the memory structure. The simulation capability allows the control circuit portion to be verified separately, enabling parallel development paths where memory structure fabrication and control circuit testing can proceed independently, significantly reducing overall development time.
Solution Approach 2:
The patent enables preliminary testing of the control circuit and sense blocks before the memory structure is fully integrated or even fabricated. By implementing simulation functionality within the control circuit, developers can perform early verification of control logic and sensing operations, identify design issues early in the development cycle, and make corrections before committing to full system fabrication, thereby reducing total development time.
3Ease of manufacture
If separate testing of control circuit and memory structure is performed, then manufacturing flexibility and optimization are improved, but integration reliability may be compromised
Solution Approach 1:
The control circuit is designed with multi-functionality, serving both as the operational control unit during normal memory operations and as a standalone testing system when simulating sensing operations. This universal design allows the same control circuit to be used in both integrated mode with memory structure and independent mode with simulation, ensuring that testing performed separately translates directly to integrated performance, thereby maintaining integration reliability while enabling manufacturing flexibility.
Data Source
AI summary
Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.