Simultaneous Zero Layer and Active Area Alignment Mark Formation

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Solution Overview

Problem

Current methods for forming alignment marks in semiconductor fabrication lack sufficient precision, particularly at the die level, as zero layer alignment marks provide only global alignment and are not adequate for forming features with high precision, necessitating the use of additional active area alignment marks that are smaller and more precise.

Innovation Solution

A method involving the simultaneous formation of zero layer alignment marks and active area alignment marks on a semiconductor wafer, where zero layer marks provide global alignment and active area marks offer precise alignment at the die level, using various lithography and etching processes to create specific patterns and recesses in the substrate, allowing for accurate positioning of subsequent layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If only zero layer alignment marks are used, then the fabrication process is simpler, but the alignment precision at the die level is insufficient

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidalignment precision at die level
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The alignment mark system is segmented into two distinct types: zero layer alignment marks for global alignment and active area alignment marks for local die-level alignment. This segmentation allows each type of mark to be optimized for its specific function, with zero layer marks providing broad coverage and active area marks providing precise local positioning.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the wafer are assigned different alignment mark characteristics. Zero layer marks are formed in regions where global alignment is needed, while active area marks are formed in specific die areas where high-precision alignment is required. This local differentiation optimizes alignment precision where needed without unnecessarily complicating the overall fabrication process.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If active area alignment marks are added to provide precise alignment, then the alignment precision improves, but the device complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoidalignment mark structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The formation of zero layer alignment marks and active area alignment marks is merged into a single integrated process flow. Both types of marks are formed simultaneously using the same lithography and etching equipment, sharing common process steps such as photoresist coating, exposure, and etching. This merging reduces the overall complexity by eliminating the need for separate processing lines.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The alignment mark formation process is designed to be multi-functional, serving both global alignment (via zero layer marks) and local alignment (via active area marks) purposes within a single process sequence. The same lithography and etching tools perform multiple functions, and the process parameters are optimized to accommodate both types of marks without requiring separate specialized equipment.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If both zero layer and active area alignment marks are formed simultaneously, then the alignment accuracy is maximized, but the fabrication time increases

Engineering Contradiction:
Improvealignment accuracyVSAvoidfabrication throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The formation of zero layer and active area alignment marks is implemented as a continuous process without interruption. The lithography step exposes both types of marks in sequence within the same exposure cycle, and the etching process immediately follows without requiring intermediate handling or equipment changes. This continuity maintains high alignment accuracy while minimizing idle time and maximizing fabrication throughput.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS10074612B2Method for forming alignment marks and structure of same
Publication Date: 2018.09.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10074612B2 patent drawing
  • US10074612B2 patent drawing
  • US10074612B2 patent drawing

AI summary

A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.