Invertible Sine-Shaping Phase Interpolator for Low-Power CDR
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Solution Overview
Problem
Clock and data recovery (CDR) systems face challenges in high-speed data applications due to the complexity and power consumption of synthesizers and phase interpolators, as well as interference issues in radio transceiver applications, particularly as data rates increase.
Innovation Solution
An apparatus and method utilizing an invertible sine-shaping filter and phase interpolator to generate sinusoidal clock signals from in-phase and quadrature-phase clock signals, with selective inversion based on an inversion control signal, to simplify phase integration and reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a frequency synthesizer and quadrature divider are used to generate high-speed clock signals, then the sampling clock signal can be generated with adequate frequency, but the system consumes relatively large power and occupies large die area
Solution Approach 1:
The patent extracts and removes the frequency synthesizer and quadrature divider from the clock generation system, replacing them with a simplified phase interpolator that directly generates the sampling clock signal from a reference clock, thereby eliminating the power-consuming components while maintaining the required clock frequency
Solution Approach 2:
Instead of generating a high-frequency clock and then dividing it down (the conventional approach), the patent inverts the approach by using a reference clock and interpolating phase to directly generate the desired sampling clock signal, avoiding the need for frequency multiplication and division stages
2Speed
If a frequency synthesizer and quadrature divider are used to generate high-speed clock signals, then the sampling clock signal can be generated with adequate frequency, but the system occupies relatively large die area
Solution Approach 1:
The patent removes the frequency synthesizer and quadrature divider components that occupy large die area, replacing them with a compact phase interpolator implementation that achieves the same clock generation function with significantly reduced area
Solution Approach 2:
The patent merges the clock generation and phase adjustment functions into a single phase interpolator component, eliminating the need for separate frequency synthesizer and quadrature divider blocks, thereby reducing overall die area
3Adaptability or versatility
If a phase interpolator with multiple weightings is used, then the phase interpolation range is increased, but the device becomes more difficult to design and consumes more power
Solution Approach 1:
The patent segments the phase interpolation function into discrete, selectively enabled pathways corresponding to different weighting combinations, allowing the device to achieve extended phase range while maintaining simple design of individual segments that can be independently optimized
Solution Approach 2:
The patent implements dynamic selection of interpolation weightings through control signals that enable or disable specific buffer pathways based on the desired phase output, allowing the system to adapt its complexity to the required phase range rather than maintaining full complexity for all operating conditions
4Adaptability or versatility
If a phase interpolator with multiple weightings is used, then the phase interpolation range is increased, but the device presents larger load to input drivers
Solution Approach 1:
The patent divides the interpolation buffers into multiple segments that can be independently enabled or disabled, so that only the necessary portion of the buffer load is activated based on the required phase interpolation, reducing the total load presented to input drivers while maintaining extended phase range capability
Solution Approach 2:
The patent implements partial activation of interpolation buffers by enabling only the specific weighting pathways needed for the current operating condition, rather than activating all buffers simultaneously, thereby achieving the required phase range with reduced driver load
5Loss of time
If interpolation buffers are kept ready for multiple weightings, then the phase interpolation response is faster, but the buffers consume significant leakage power even when inactive
Solution Approach 1:
The patent implements periodic or conditional activation of interpolation buffers based on the required phase weighting, using control signals to enable buffers only when their corresponding weighting is needed, thereby eliminating continuous leakage power consumption while maintaining fast response through pre-positioned control logic
Solution Approach 2:
The patent removes the need for continuously powered standby buffers by extracting only the essential buffering function and implementing it through selectively activated pathways, eliminating the leakage power waste associated with keeping all buffers in a ready state
Data Source
AI summary
Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, an apparatus includes an invertible sine shaping filter configured to receive an in-phase clock signal, a quadrature-phase clock signal, and an inversion control signal. The invertible sine-shaping filter is further configured to filter the in-phase and quadrature-phase clock signals to generate sinusoidal in-phase and quadrature-phase clock signals. The invertible sine-shaping filter is further configured to selectively invert one or both of the in-phase and quadrature-phase clock signals based on an inversion control signal. The apparatus further includes a phase interpolator configured to generate an interpolated clock signal based on a weighted sum of the selectively inverted sinusoidal in-phase clock signal and the quadrature-phase sinusoidal clock signal. The in-phase clock signal and the quadrature-phase clock signal have a quadrature-phase relationship.