Single-Carrier Burst Structure for Parallel Equalization at Lower Clock Rates
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Solution Overview
Problem
High clock frequencies required for very high data rates in millimeter-wave UWB communications lead to impractical operation and high power dissipation, especially in mobile devices, due to the need for integer-multiple clock frequencies for decision feedback equalization.
Innovation Solution
A method involving generating data streams with known sequences inserted between sub-blocks, allowing for parallel equalizations that reduce the required clock frequency to a fraction of the input signal data rate, facilitating efficient channel estimation and equalization in wireless communication systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high clock frequencies are used for signal equalization in high data rate wireless communication systems, then data transmission rate is improved, but power dissipation increases prohibitively
Solution Approach 1:
The data block is divided into multiple sub-blocks with known sequences inserted between them. This segmentation enables parallel processing of multiple sub-blocks simultaneously at a reduced clock frequency, rather than processing the entire block sequentially at high frequency, thereby maintaining high data transmission rates while reducing power consumption.
Solution Approach 2:
The patent transitions from time-domain sequential processing to frequency-domain parallel processing by inserting known sequences between sub-blocks. This allows the receiver to perform parallel equalization operations in the frequency domain using FFT-based methods, effectively trading time for frequency processing to reduce clock frequency requirements while maintaining throughput.
2Measurement precision
If high clock frequencies are used for decision feedback equalization, then signal detection accuracy is maintained, but device complexity and implementation feasibility deteriorate
Solution Approach 1:
By segmenting the data block into sub-blocks separated by known sequences, the patent enables independent parallel processing of each sub-block. This reduces the computational burden on individual equalization operations and makes the system more implementable while maintaining detection accuracy through multiple parallel estimation paths.
Solution Approach 2:
Known sequences are inserted between sub-blocks before transmission, providing pre-established reference points that the receiver can use for channel estimation and equalization. This preliminary action simplifies the detection process by providing known reference data for comparison and reduces the complexity of blind equalization methods.
Data Source
AI summary
Certain aspects of the present disclosure relate to a method for employing a special format for transmitting data blocks which allows parallel equalizations at a receiver. By applying parallel equalization operations, a clock at the receiver can operate at a fraction of the input signal's data rate, which is more practical in the case of very high data rates while power dissipation is also reduced.