Single-Chip Power Diode Layout for Lower Switching Losses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional power diodes for fast switching applications face challenges such as increased leakage current, reduced recombination efficiency, and worsened diode softness due to techniques like platinum doping and structured cathodes, which limit parallel connection and increase switching losses.
Innovation Solution
A single chip power diode design featuring an active region with a drift region and edge termination region, where only a part of the diode chip area is electrically active, allowing for higher current density and improved thermal performance, and including inactive subregions with blocking areas to prevent current crossing, optimizing dynamic performance and reducing switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If carrier lifetime killing techniques like platinum doping are used to reduce switching losses, then switching losses are reduced, but the temperature coefficient of the diode forward voltage becomes more negative which limits parallel connection
Solution Approach 1:
The patent divides the anode region into multiple independently controllable segments or zones. Each segment can be individually doped with platinum or other carrier lifetime killing materials at different concentrations, allowing independent optimization of switching performance while maintaining flexibility for parallel connections through uniform overall characteristics.
Solution Approach 2:
The patent applies carrier lifetime killing techniques locally in specific regions of the anode rather than uniformly throughout. This allows high recombination efficiency in targeted areas to reduce switching losses while maintaining better overall forward voltage characteristics through controlled spatial distribution of doping concentrations.
2Loss of energy
If platinum doping is used to reduce switching losses, then switching losses are reduced, but recombination efficiency is reduced at elevated temperature leading to increased stored charge
Solution Approach 1:
The patent combines platinum doping with damage implantation techniques (using Argon or Helium) to create a composite approach for carrier lifetime control. This multi-method doping strategy achieves effective recombination at operating temperatures while mitigating the temperature-dependent efficiency reduction caused by platinum alone, through synergistic effects of different doping mechanisms.
Solution Approach 2:
The patent optimizes the concentration and distribution parameters of platinum dopants, using lower overall concentrations combined with localized high-concentration regions. This parameter optimization maintains effective switching loss reduction while improving high-temperature recombination efficiency by preventing excessive carrier accumulation in uniformly heavily doped regions.
3Loss of energy
If a structured cathode is used to reduce switching losses, then switching losses are reduced, but carrier concentration at the backside is reduced which leads to worse diode softness performance
Solution Approach 1:
The patent moves the carrier lifetime control mechanism from the cathode region to the anode region, effectively changing the spatial dimension where recombination occurs. By implementing platinum doping and damage implantation in the anode rather than structuring the cathode, the patent achieves switching loss reduction without adversely affecting carrier concentration at the cathode backside, thereby preserving diode softness performance.
4Loss of energy
If damage implantation is used to reduce carrier concentration, then switching losses are reduced, but leakage current is increased
Solution Approach 1:
The patent optimizes the damage implantation parameters including ion type (Argon or Helium), energy levels, and dosage to achieve effective carrier concentration reduction for switching loss mitigation while controlling the extent of crystal damage. By carefully tuning these parameters and combining with annealing processes, the patent reduces leakage current caused by excessive damage while maintaining effective carrier lifetime control.
Data Source
AI summary
A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.